Patents by Inventor Yangbo Yi
Yangbo Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180054128Abstract: Disclosed are a control method and a control circuit for a switching power supply, said switching power supply comprises a secondary controller and a secondary MOS M2 connected between a load and a secondary winding of a transformer. The present invention is used for detecting a working state of the secondary winding of a transformer and a type of a communication signal transmitted by a load, and for generating a switching pulse signal VG in a Reset Time of an on/off cycle according to the type of the communication signal; the primary controller detects a variation amplitude of the transiently varied signal of the voltage drop at the pin FB in the Reset Time; if the variation amplitude of the transiently varied signal is greater than a pre-set value ?Vref, the primary controller judges that the signal is a communication signal, and records the communication signal.Type: ApplicationFiled: February 9, 2017Publication date: February 22, 2018Inventors: Haisong LI, Yangbo YI, Changshen ZHAO, Wenliang LIU
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Publication number: 20170338811Abstract: Disclosed is a high voltage power system with enable control, comprising a high voltage start-up circuit, a PWM control module, and a driving module; the high voltage start-up circuit comprises a first transistor, a third transistor, a fourth transistor, a resistor, a diode, a VDD detection unit and an I/O interface unit; the high voltage start-up circuit is controlled by an input of a pin EN; when the pin EN is set, the high voltage start-up circuit stops working; the power system is shut off and doesn't restart, and enters a zero standby state; when the pin EN is reset, the high voltage start-up circuit restores to work, and the power system restarts and enters a normal working state. The power system having the high voltage start-up circuit with enable control has characteristics that the standby input power consumption and standby input current are both close to zero.Type: ApplicationFiled: November 9, 2016Publication date: November 23, 2017Inventors: HAISONG LI, CHANGSHEN ZHAO, YANGBO YI, WENLIANG LIU, ZHIJUN WU
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Patent number: 9812945Abstract: The present disclosure relates to a circuit structure for enhancing EFT immunity of primary side converter, including a power ground and a feedback voltage detecting block, a feedback current detecting block, a controller, a PWM driving block, a high voltage starting block, a starting unit, a circuit for enhancing EFT immunity of primary side converter, a power MOS transistor, and an OR gate configured to perform a logical OR of an off-time calculated theoretically and an off-time output by an off-time control block. The present disclosure enhances EFT immunity effectively and improves the dynamic characteristics of the primary side converter.Type: GrantFiled: October 12, 2015Date of Patent: November 7, 2017Assignee: Wuxi Chipown Micro-Electronics, LimitedInventors: Haisong Li, Ping Tao, Changshen Zhao, Yangbo Yi
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Patent number: 9800164Abstract: A compensation circuit for constant output voltage is disclosed. The compensation circuit comprises a current source, a first switch, a controllable current source, a second switch, a logic NOT gate, a CV loop control module, and an input voltage detection module. The compensation circuit ensures a normal start-up, and substantially no additional power dissipation of the converter is generated at no load. Furthermore, the compensation circuit adjusts a compensation current according to at least one of a detected input voltage of the power supply converter and a working mode of the transformer, to obtain better precision of constant output voltage. The compensation circuit can be applied to occasions where extremely small standby input power dissipation or extremely high precision of constant output voltage is required.Type: GrantFiled: November 16, 2016Date of Patent: October 24, 2017Assignee: SUZHOU POWERON IC DESIGN CO., LTDInventors: Haisong Li, Changshen Zhao, Yangbo Yi, Wenliang Liu
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Publication number: 20170077695Abstract: Disclosed is a short-circuit protection circuit for a voltage sampling resistor of a primary side converter, comprising a high voltage power transistor, a high voltage starting resistor, a first voltage dividing resistor of a port VDD, a second voltage dividing resistor of the port VDD, an NMOS transistor, a diode, a first comparator, a second comparator, a third comparator, a time delay circuit, a filter, a first logic circuit, a second logic circuit, a current supply, a first AND gate and a first inverter. The chip of the present disclosure is capable of correctly and effectively detecting whether the sampling resistor is shorted or not before the chip works normally, thereby avoiding the risk of damaging the chip by large current from the voltage feedback port FB due to turn-on of the switching transistor when the upper voltage sampling resistor is shorted, and greatly reducing the input power.Type: ApplicationFiled: February 18, 2016Publication date: March 16, 2017Inventors: HAISONG LI, CHANGSHEN ZHAO, YANGBO YI
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Publication number: 20160336851Abstract: The present disclosure relates to a circuit structure for enhancing EFT immunity of primary side converter, including a power ground and a feedback voltage detecting block, a feedback current detecting block, a controller, a PWM driving block, a high voltage starting block, a starting unit, a circuit for enhancing EFT immunity of primary side converter, a power MOS transistor, and an OR gate configured to perform a logical OR of an off-time calculated theoretically and an off-time output by an off-time control block. The present disclosure enhances EFT immunity effectively and improves the dynamic characteristics of the primary side converter.Type: ApplicationFiled: October 12, 2015Publication date: November 17, 2016Inventors: Haisong LI, Ping TAO, Changshen ZHAO, Yangbo YI
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Patent number: 9431892Abstract: A high voltage start-up circuit with adjustable start-up time, wherein, the drain electrode of the first NMOS transistor is connected with a first terminal of the first resistor, a gate electrode of the second NMOS transistor and a negative terminal of the diode; a source electrode of the first NMOS transistor, together with a positive terminal of the diode, is connected to the power ground; a drain electrode of the second NMOS transistor, together with a second terminal of the first resistor, is connected with a port SW of a chip; a source electrode of the second NMOS transistor, together with a first terminal of the second resistor, is connected with a power port VDD of the chip. The circuit can adjust the start-up time and the restart time of the chip flexibly.Type: GrantFiled: December 21, 2015Date of Patent: August 30, 2016Assignee: SUZHOU POWERON IC DESIGN CO., LTDInventors: Haisong Li, Changshen Zhao, Ping Tao, Yangbo Yi
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Patent number: 9007099Abstract: A semiconductor device with a current sampler and a start-up structure, comprises first, second and third high-voltage transistors, and a resistor, wherein: a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor, a drain terminal of the third transistor and one end of the resistor; a source terminal of the first transistor is grounded, and a gate terminal of the first transistor is connected to a gate terminal of the second transistor; the other end of the resistor is connected to a gate terminal of the third transistor; wherein the resistor is wound and formed in a common voltage withstand region of the first transistor, the second transistor and the third transistor, or in a voltage withstand region of the first transistor only, or in the voltage withstand region of the third transistor only.Type: GrantFiled: March 27, 2014Date of Patent: April 14, 2015Assignee: Suzhou Poweron IC Design Co., LtdInventors: Yangbo Yi, Haisong Li, Ping Tao, Wengao Chen, Lixin Zhang
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Publication number: 20140362488Abstract: A short-circuit protection structure comprises first and second high-voltage transistors, a control circuit, a first current sampling resistor for the first transistor and a second current sampling resistor for the second transistor. The control circuit controls switching period and duty cycle of the first transistor and the second transistor, a drain terminal of the first transistor is connected to a drain terminal of the second transistor, a source terminal of the first transistor is connected to the first current sampling resistor, and a source terminal of the second transistor is connected to the second current sampling resistor; a gate terminal of the first transistor and a gate terminal of the second transistor are connected to a driver stage of the control circuit. The size of the second transistor is smaller than the first transistor, and the current of the first transistor is sampled by the second transistor.Type: ApplicationFiled: March 26, 2014Publication date: December 11, 2014Inventors: Ping TAO, Haisong Li, Hualong Zhuang, Yangbo Yi
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Publication number: 20140292380Abstract: A semiconductor device with a current sampler and a start-up structure, comprises first, second and third high-voltage transistors, and a resistor, wherein: a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor, a drain terminal of the third transistor and one end of the resistor; a source terminal of the first transistor is grounded, and a gate terminal of the first transistor is connected to a gate terminal of the second transistor; the other end of the resistor is connected to a gate terminal of the third transistor; wherein the resistor is wound and formed in a common voltage withstand region of the first transistor, the second transistor and the third transistor, or in a voltage withstand region of the first transistor only, or in the voltage withstand region of the third transistor only.Type: ApplicationFiled: March 27, 2014Publication date: October 2, 2014Inventors: Yangbo YI, Haisong Li, Ping Tao, Wengao Chen, Lixin Zhang
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Patent number: 8482064Abstract: A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.Type: GrantFiled: June 11, 2012Date of Patent: July 9, 2013Assignee: Suzhou Poweron IC Design Co., Ltd.Inventors: Yangbo Yi, Haisong Li, Qin Wang, Ping Tao, Lixin Zhang
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Publication number: 20130069155Abstract: A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.Type: ApplicationFiled: June 11, 2012Publication date: March 21, 2013Applicant: Suzhou Poweron IC Design Co., LtdInventors: Yangbo YI, Haisong LI, Qin WANG, Ping TAO, Lixin ZHANG
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Patent number: 7557634Abstract: The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit.Type: GrantFiled: October 20, 2004Date of Patent: July 7, 2009Assignee: Southeast UniversityInventors: Longxing Shi, Weifeng Sun, Haisong Li, Shengli Lu, Yangbo Yi
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Publication number: 20070205820Abstract: The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit.Type: ApplicationFiled: October 20, 2004Publication date: September 6, 2007Inventors: Longxing Shi, Weifeng Sun, Haisong Li, Yangbo Yi