Abstract: A semiconductor device a plurality of semiconductor patterns on a substrate and extending in a first direction parallel to an upper surface of the substrate, the plurality of semiconductor patterns are spaced apart in a third direction, a bit line extending in the third direction and electrically connected to a first end of each of the plurality of semiconductor patterns, a plurality of word lines on the plurality of semiconductor patterns and extending in a second direction parallel to the upper surface of the substrate, a plurality of first electrodes extending in the first direction and spaced apart in the third direction, each of the plurality of first electrodes has a first end electrically connected to a second end of a corresponding semiconductor pattern and a supporter extending in the third direction and covering a second end of each of the plurality of first electrodes.

Abstract: A semiconductor device includes a gate electrode extending on a substrate in a first direction, a semiconductor pattern extending in a second direction crossing the first direction, and penetrating the gate electrode, and a gate insulating layer between the gate electrode and the semiconductor pattern. The semiconductor pattern has side surfaces facing away from each other in the first direction, and an upper surface and a lower surface facing away from each other in a third direction. The gate electrode includes conductive sub-patterns respectively disposed on the side surfaces of the semiconductor pattern, and spaced apart from each other in the first direction and a conductive pattern extending in the first direction to cover the upper and lower surfaces of the semiconductor pattern and to cover the conductive sub-patterns. The conductive sub-patterns have a work-function different from that of the conductive pattern.

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined therein, a first word line structure including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the first word line structure being buried in the substrate, and crossing a first active region of the plurality of active regions, a second word line structure including a second word line and a second gate dielectric film surrounding the second word line, the second word line structure being buried in the substrate and separated from the first word line structure, and crossing the first active region, a direct contact partially passing through the first active region and the first word line structure and contacting the oxide semiconductor channel layer, and a bit line contacting the direct contact.

Abstract: A semiconductor device including a substrate; storage node contacts on the substrate; lower electrode structures on the storage node contacts; a supporter structure on an external side surface of the lower electrode structures and connecting adjacent lower electrode structures to each other; a dielectric layer on the lower electrode structures and the supporter structure; and an upper electrode structure on the dielectric layer, wherein the lower electrode structures each include a pillar portion in contact with the storage node contacts; and a cylinder portion on the pillar portion, the pillar portion includes a first lower electrode layer having a cylindrical shape and having a lower surface and a side surface; and a first portion covering at least an internal wall of the first lower electrode layer, and the cylinder portion includes a second portion extending from the first portion and covering an upper end of the first lower electrode layer.

Abstract: A three-dimensional (3D) semiconductor device may include a semiconductor pattern that is on a substrate and extends in a first direction including a first edge portion, a second edge portion, and a channel region between the first edge portion and the second edge portion, a word line that extends around the channel region and extends in a second direction, and a bit line that is on a first side surface of the first edge portion of the semiconductor pattern and extends in a third direction. The first edge portion includes a first end adjacent to the first side surface, and a first thickness of the first end in the third direction is greater than a first center thickness of a center portion of the first edge portion in the third direction.

Abstract: A method of manufacturing an integrated circuit device includes forming a mold structure, which has a mold layer and a support layer sequentially stacked, on a substrate, forming a vertical hole through the mold structure in a vertical direction and a bowing space extending outward from the vertical hole in a horizontal direction in a first vertical level area, exposing the vertical hole and the bowing space to a preprocessing atmosphere to make the support layer have a first surface state and the mold layer have a second surface state different from the first surface state, forming a bowing complementary pattern filling the bowing space by a selective deposition process using the difference between the first surface state and the second surface state, and forming a lower electrode in the vertical hole and in contact with the mold layer, the support layer, and the bowing complementary pattern.

Abstract: A method of manufacturing an integrated circuit device includes forming a mold structure, which has a mold layer and a support layer sequentially stacked, on a substrate, forming a vertical hole through the mold structure in a vertical direction and a bowing space extending outward from the vertical hole in a horizontal direction in a first vertical level area, exposing the vertical hole and the bowing space to a preprocessing atmosphere to make the support layer have a first surface state and the mold layer have a second surface state different from the first surface state, forming a bowing complementary pattern filling the bowing space by a selective deposition process using the difference between the first surface state and the second surface state, and forming a lower electrode in the vertical hole and in contact with the mold layer, the support layer, and the bowing complementary pattern.

Abstract: An integrated circuit device includes a lower electrode above a substrate, a plurality of insulating support patterns supporting the lower electrode and spaced apart from each other in a vertical direction, a plurality of bridge patterns each having a thickness less than a thickness of each of the plurality of insulating support patterns in the vertical direction and respectively interposed between the plurality of insulating support patterns and the lower electrode, a capacitor dielectric layer covering the lower electrode, the plurality of insulating support patterns, and the plurality of bridge patterns, and an upper electrode facing the lower electrode with the capacitor dielectric layer therebetween.

Abstract: A semiconductor device includes a lower structure including conductive regions; a capacitor including first electrode structures electrically connected to the conductive regions of the lower structure, a dielectric layer covering the first electrode structures, and a second electrode structure on the dielectric layer; and an upper support pattern in contact with the first electrode structures, wherein each of the first electrode structures includes a first electrode region extending vertically; and a second electrode region extending upwardly from the first electrode region and having a side surface not vertically aligned with a side surface of the first electrode region, and wherein the upper support pattern includes a first layer covering upper surfaces of the second electrode regions of the first electrode structures and connected to each other; and a second layer on the first layer and including a material different from a material of the first layer.

Abstract: A semiconductor memory device includes a conductive pattern on a substrate, a lower electrode connected to the conductive pattern and including first and second portions, one or more electrode side wall supports supporting the lower electrode and contacting a side wall of the lower electrode, an electrode capping support disposed on the lower electrode and contacting an upper face of the lower electrode, a capacitor dielectric film on the lower electrode, the electrode side wall supports, and the electrode capping support, and an upper electrode on the capacitor dielectric film. The first portion of the lower electrode has an increasing width in the first d in a second direction increases as it goes away from the conductive pattern, and a slope of the side wall of the first portion of the lower electrode is different from a slope of the side wall of the second portion of the lower electrode.

Abstract: Methods of forming a semiconductor device may include: providing a substrate on which a layer is formed; forming a lower hard-mask layer, which includes silicon, on the layer; forming an upper hard-mask pattern, which includes oxide, on the lower hard-mask layer; forming a lower hard-mask pattern by etching the lower hard-mask layer using the upper hard-mask pattern as an etch mask and using an etching gas that includes a metal-chloride-based first gas and a nitride-based second gas; and forming a plurality of contact holes in the layer by etching the material layer using the lower hard-mask pattern as an etch mask.

Abstract: A semiconductor memory device includes a substrate having a memory cell region and a plurality of capacitor structures in the memory cell region of the substrate, each of the plurality of capacitor structures including a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the lower electrode includes a first lower electrode, a second lower electrode above the first lower electrode, and a connecting lower electrode connecting a top end of the first lower electrode to a bottom end of the second lower electrode, wherein the upper electrode includes a bent upper electrode overlapping the connecting lower electrode in a horizontal direction, and the bent upper electrode includes a bent portion.

Abstract: A semiconductor device includes; a lower structure, lower electrodes on the lower structure, wherein each lower electrode includes a first lower electrode and a second lower electrode on the first lower electrode and electrically connected to the first lower electrode, an upper electrode covering the lower electrodes, and a dielectric film between the lower electrodes and the upper electrode, wherein the first lower electrode includes a pillar portion and a protruding portion on the pillar portion, wherein protruding portion has a complex shape that contacts the second lower electrode.

Abstract: An integrated circuit (IC) device may include a conductive area on a substrate; a first electrode connected to the conductive area on the substrate, a width of the first electrode in a lateral direction gradually increasing toward the substrate; a second electrode on the substrate, the second electrode including a silicon germanium (SiGe) film, the SiGe film surrounding the first electrode; and a dielectric film between the first electrode and the second electrode. A content of a component of the SiGe film may vary according to a distance from the substrate.

Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined therein, a first word line structure including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the first word line structure being buried in the substrate, and crossing a first active region of the plurality of active regions, a second word line structure including a second word line and a second gate dielectric film surrounding the second word line, the second word line structure being buried in the substrate and separated from the first word line structure, and crossing the first active region, a direct contact partially passing through the first active region and the first word line structure and contacting the oxide semiconductor channel layer, and a bit line contacting the direct contact.

Abstract: A method of manufacturing an integrated circuit device includes forming a mold structure, which has a mold layer and a support layer sequentially stacked, on a substrate, forming a vertical hole through the mold structure in a vertical direction and a bowing space extending outward from the vertical hole in a horizontal direction in a first vertical level area, exposing the vertical hole and the bowing space to a preprocessing atmosphere to make the support layer have a first surface state and the mold layer have a second surface state different from the first surface state, forming a bowing complementary pattern filling the bowing space by a selective deposition process using the difference between the first surface state and the second surface state, and forming a lower electrode in the vertical hole and in contact with the mold layer, the support layer, and the bowing complementary pattern.

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

Abstract: A semiconductor device including a substrate; storage node contacts on the substrate; lower electrode structures on the storage node contacts; a supporter structure on an external side surface of the lower electrode structures and connecting adjacent lower electrode structures to each other; a dielectric layer on the lower electrode structures and the supporter structure; and an upper electrode structure on the dielectric layer, wherein the lower electrode structures each include a pillar portion in contact with the storage node contacts; and a cylinder portion on the pillar portion, the pillar portion includes a first lower electrode layer having a cylindrical shape and having a lower surface and a side surface; and a first portion covering at least an internal wall of the first lower electrode layer, and the cylinder portion includes a second portion extending from the first portion and covering an upper end of the first lower electrode layer.

Abstract: A semiconductor device includes a substrate having a cell array region and a peripheral region, lower electrodes disposed on the cell array region, at least one supporter layer contacting the lower electrodes, a dielectric layer covering the lower electrodes and the at least one supporter layer, an upper electrode covering the dielectric layer, an interlayer insulating layer covering an upper surface and a side surface of the upper electrode, a peripheral contact plug passing through the interlayer insulating layer on the peripheral region of the substrate, and a first oxide layer between the upper electrode and the peripheral contact plug. The upper electrode includes at least one protruding region protruding in a lateral direction from the cell array region toward the peripheral region. The first oxide layer is disposed between the at least one protrusion region and the peripheral contact plug.