Abstract: Methods and systems for equalizing signals are disclosed. In an example, a method for equalizing a digital signal at an equalizer, comprises: receiving, at the equalizer, a plurality of samples of the signal in a plurality of unit intervals (UIs) of a channel response of the digital signal, the plurality of samples comprising a first plurality of samples of a primary response and a second plurality of samples of one or more reflection responses; equalizing, by the equalizer, the first plurality of samples using a first set bitwidth; equalizing the second plurality of samples using one or more further set bitwidths, wherein the first set bitwidth is greater than each of the one or more further set bitwidths; and generating, by the equalizer, an equalized digital signal.

Abstract: Methods and systems for equalizing signals are disclosed. In an example, a method for equalizing a digital signal at an equalizer, comprises: receiving, at the equalizer, a plurality of samples of the signal in a plurality of unit intervals (UIs) of a channel response of the digital signal, the plurality of samples comprising a first plurality of samples of a primary response and a second plurality of samples of one or more reflection responses; equalizing, by the equalizer, the first plurality of samples using a first set bitwidth; equalizing the second plurality of samples using one or more further set bitwidths, wherein the first set bitwidth is greater than each of the one or more further set bitwidths; and generating, by the equalizer, an equalized digital signal.

Abstract: Systems and methods are disclosed for improving digital feed-forward data recovery of high speed data from a received data stream in a data transceiver or receiver where the receiver clock is asynchronous to the transmitter clock used to transmit the received data stream. In one example, the received data stream is oversampled using N evenly-spaced multi-phase clocks. The oversampled data are packed into a data block. Data transition edges of the oversampled data in the data blocks with respect to multi-phase clocks are tracked. The tracked data transition edges are used to determine the length of a decision window and to further divide the oversampled data into groups of bits that are hypothesized to be samples of the same received data symbol. Bit mapping is performed on the decision window to recover the received data symbol. By tracking the movement of data transition edges, the technique enhances data recovery capability.

Abstract: Systems and methods are disclosed for improving the accuracy of phase spacing of multiphase clocks. In one example, method includes receiving a reference clock having a first frequency and sampling the reference clock with a plurality of multiphase clocks having a second frequency to generate a plurality of samples. The second frequency is a non-integer multiple of the first frequency. The method also includes detecting transitions of the reference clock occurring between the samples generated from a plurality of pairs of the multiphase clocks and counting the transitions to generate a transition count for each pair of the multiphase clocks. The method also includes summing a set of the transition counts to generate a measured phase for a first multiphase clock, calculating a reference phase for the first multiphase clock, and generating a phase skew value for the first multiphase clock based on the measured phase and the reference phase.