Abstract: An airbridge arrangement method for a chip layout includes obtaining location information of n points defining routing of a coplanar waveguide (CPW) to be arranged in the chip layout, n being an integer greater than 1. The method further includes automatically determining a skeleton line of the CPW according to the location information of the n points and according to the chip layout, the skeleton line of the CPW being a center line of a center conductor of the CPW. The method further includes automatically arranging airbridges on the chip layout according to the skeleton line of the CPW.

Abstract: In a routing method, an initial chip layout and routing planning information corresponding to the initial chip layout are obtained. The routing planning information includes planning information of a first site in the initial chip layout. The planning information indicates a location region, a routing orientation, and a predefined connection path. A first end of the predefined connection path is connected to the first site. According to the location region and the routing orientation, a first route segment connecting a second site of the initial chip layout and a second end of the predefined connection path is determined. According to the predefined connection path, a second route segment connecting the second end of the predefined connection path and the first site is determined. According to the first route segment and the second route segment, a connection route between the second site and the first site is generated.

Abstract: A method of designing an air bridge layout in a circuit layout is performed by a computer device, and in particular, relates to the field of chip technologies. The method includes: obtaining position information of skeleton lines of CPW lines based on position information of the coplanar waveguide CPW lines in the circuit layout, each skeleton line being a center line of a corresponding CPW line; obtaining an interweave pair from the skeleton lines of the CPW lines based on the position information of the skeleton lines of the CPW lines, the interweave pair including two parallel skeleton line segments; and deploying air bridges on the circuit layout, the air bridges being deployed along the skeleton lines, and the air bridges on the two skeleton lines in the interweave pair being arranged in a staggered manner (340). According to the foregoing solution, interferences between air bridges on different CPW lines are reduced, and a success rate of subsequent circuit fabrication is improved.