Abstract: Fingerprint identification modules, methods for forming the fingerprint identification modules and electronic devices are provided. The method may include providing a substrate, containing a signal process circuit formed therein; providing a carrier substrate; forming one or more piezoelectric transducers on the carrier substrate, wherein a piezoelectric transducer of the one or more piezoelectric transducers includes a first electrode, a piezoelectric layer on the first electrode and a second electrode on the piezoelectric layer; forming a permanent bonding layer, containing one or more cavities, on one of the carrier substrate and the substrate; bonding the carrier substrate with the substrate using the permanent bonding layer, wherein the permanent bonding layer is between the one or more piezoelectric transducers and the substrate, and each piezoelectric transducer covers one cavity; and removing the carrier substrate.

Abstract: In this invention, an imaging module and a method for fabricating it are provided. By designing first and second electrodes, a movable part of the second electrode is connected to the flexible part. Upon a voltage being applied to the first and second electrodes, the second electrode moves toward the first electrode, resulting in a stretch and hence a shape change of a flexible part. As a result, the imaging module undergoes a change in terms of focal length, amount of admitted light and/or admissible range of angle of incident light. In particular, a motion controller incorporating the first and second electrodes can be easily fabricated by semiconductor processes to a very small size, making the imaging module very suitable for use in electronic terminals such as mobile phones with confined enclosure spaces.

Abstract: A CMOS image sensor package module, method for forming same, and imaging device. In the CMOS image sensor package module, a signal processing chip (200) and a DRAM chip (600) are bonded to a pixel circuit substrate (100). The signal processing chip (200) and the DRAM chip (600) are electrically connected by a first interconnection structure (210) and each of a readout circuit in the pixel circuit substrate (100), the signal processing chip (200) and the DRAM chip (600) is electrically connected to a second interconnection structure (220), and the second interconnection structure (220) is electrically connected to a rewiring layer (500). This structurally optimized package module allows digital image signals output from the readout circuit to be first cached in the DRAM chip (600) and then output therefrom to the signal processing chip (200) for processing.

Abstract: A CMOS image sensor packaging structure and a fabrication method thereof, and a camera device are provided. The packaging structure includes a pixel circuit substrate including a photosensitive region and a readout circuit region. A pixel array is disposed in the photosensitive region, and the readout circuit including a circuit interconnection terminal is disposed in the readout circuit region. The pixel circuit substrate includes a first surface and a second surface that are oppositely disposed. The packaging structure also includes a bonding layer disposed on the first surface. Moreover, the packaging structure includes a signal processing chip disposed above the first surface through the bonding layer. The signal processing chip includes a chip interconnection terminal. In addition, the packaging structure includes an interconnection structure electrically connected to the chip interconnection terminal and the circuit interconnection terminal.

Abstract: Fingerprint identification modules, methods for forming the fingerprint identification modules and electronic devices are provided. The method may include providing a substrate, containing a signal process circuit formed therein; providing a carrier substrate; forming one or more piezoelectric transducers on the carrier substrate, wherein a piezoelectric transducer of the one or more piezoelectric transducers includes a first electrode, a piezoelectric layer on the first electrode and a second electrode on the piezoelectric layer; forming a permanent bonding layer, containing one or more cavities, on one of the carrier substrate and the substrate; bonding the carrier substrate with the substrate using the permanent bonding layer, wherein the permanent bonding layer is between the one or more piezoelectric transducers and the substrate, and each piezoelectric transducer covers one cavity; and removing the carrier substrate.

Abstract: A CMOS image sensor packaging structure and a fabrication method thereof, and a camera device are provided. The packaging structure includes a pixel circuit substrate including a photosensitive region and a readout circuit region. A pixel array is disposed in the photosensitive region, and the readout circuit including a circuit interconnection terminal is disposed in the readout circuit region. The pixel circuit substrate includes a first surface and a second surface that are oppositely disposed. The packaging structure also includes a bonding layer disposed on the first surface. Moreover, the packaging structure includes a signal processing chip disposed above the first surface through the bonding layer. The signal processing chip includes a chip interconnection terminal. In addition, the packaging structure includes an interconnection structure electrically connected to the chip interconnection terminal and the circuit interconnection terminal.

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The semiconductor device also includes a plurality of transistors on the second semiconductor substrate, a deep trench isolation having a bottom at a surface of the first semiconductor substrate in the second region, the deep trench isolation exposing a sidewall of the second semiconductor substrate and a sidewall of the buried insulating layer, and a dielectric capping layer filling the deep trench isolation and covering the plurality of transistors on the second semiconductor substrate.

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

Abstract: An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.

Abstract: A multi-way valve includes a plurality of parallel combination valves for controlling corresponding actuators (4-1-4-5). Each combination valve comprises proportional throttle valves (2-1-2-5) and reversing valves (3-1-3-5). An oil inlet of the proportional throttle valve is communicated with a main oil inlet (P), and an oil outlet of the proportional throttle valve is communicated with an oil inlet of the reversing valve. An oil outlet of the reversing valve is communicated with the main oil return port (T). Wherein, each combination valve further comprises a one-way control valve (9-1-9-5, 10-1-10-5) for obtaining the load pressure of corresponding actuator. One side of the one-way control valve is communicated with a pipeline between the proportional throttle valve and the actuator. The multi-way valve further includes a control element (8) which receives the load pressure fed back by each one-way control valve and responds to the load pressure to control the supply of hydraulic oil for the actuators.

Abstract: An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.

Abstract: An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.

Abstract: An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.