Patents by Inventor Yang-Ming Chen

Yang-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual micro-electro mechanical system and manufacturing method thereof
    Patent number: 11993512
    Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng, Yi-Chuan Teng
  • Guided power grid augmentation system and method
    Patent number: 11829698
    Abstract: A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: November 28, 2023
    Assignee: Synopsys, Inc.
    Inventors: Hsiang-Wen Chang, Yang-Ming Chen
  • GUIDED POWER GRID AUGMENTATION SYSTEM AND METHOD
    Publication number: 20220050952
    Abstract: A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 17, 2022
    Inventors: Hsiang-Wen Chang, Yang-Ming Chen
  • Rail block context generation for block-level rail voltage drop analysis
    Patent number: 11022634
    Abstract: A system is disclosed that includes a memory and a processor to perform operations, including analyzing rail voltage drop for a full-chip to identify an IR drop violation in a block design of the full-chip. The operations include performing a block-level rail voltage drop analysis for the block design and generating a revised block design corresponding to the block design in which the IR drop violation is identified. The operations include performing a block-level rail voltage drop analysis on the revised block design to verify that the IR drop violation is fixed and integrating the revised block design into the full-chip to replace the block design upon verifying that the IR drop violation is fixed. The operations include performing the rail voltage drop analysis for the full-chip comprising the revised block design.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Synopsys, Inc.
    Inventors: Mu-Shun Lee, Yang-Ming Chen, Youxin Gao