Patents by Inventor Yangming Liu
Yangming Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978713Abstract: The present disclosure generally relates to a flip chip assembly having a bump that reduces stress levels in a low-k dielectric layer in the flip chip. Rather than having a single, large area plateau that interfaces with a large corresponding opening of an insulating layer in the flip chip, the bump includes a plurality of much smaller pillars that interface with a corresponding plurality of openings in the insulating layer. In so doing, the low-k layer within the flip chip experiences much less stress and hence, fewer failures.Type: GrantFiled: May 20, 2022Date of Patent: May 7, 2024Assignee: Western Digital Technologies, Inc.Inventors: Shenghua Huang, Yangming Liu, Bo Yang, Ning Ye
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Patent number: 11961778Abstract: A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.Type: GrantFiled: September 27, 2021Date of Patent: April 16, 2024Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Shenghua Huang, Yangming Liu, Bo Yang, Ning Ye
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Publication number: 20230402361Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and reinforcing blocks on the substrate. The reinforcing blocks may be provided at positions on the substrate where mechanical stresses develop in the device during singulation, such as at curves and/or discontinuous points around the outline of the substrate, to add strength to the substrate.Type: ApplicationFiled: June 14, 2022Publication date: December 14, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Shenghua Huang, Binbin Zheng, Shaopeng Dong, Songtao Lu, Rui Guo, Yangming Liu, Bo Yang, Ning Ye
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Publication number: 20230395446Abstract: A semiconductor device including one or more support structures for supporting a semiconductor-die stack having a region that overhangs a substrate. In an example embodiment, the support structures may be implemented using suitably shaped pieces of relatively thick round or ribbon wire attached to metal pads on the substrate. During the encapsulation operation, the one or more support structures may counteract a bending force applied to the semiconductor-die stack by a flow of the molding compound. At least some embodiments may beneficially be used, e.g., to enable high-yield fabrication of devices having sixteen or more stacked memory dies.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Inventors: Yangming Liu, Shenghua Huang, Bo Yang, Ning Ye
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Publication number: 20230378112Abstract: The present disclosure generally relates to a flip chip assembly having a bump that reduces stress levels in a low-k dielectric layer in the flip chip. Rather than having a single, large area plateau that interfaces with a large corresponding opening of an insulating layer in the flip chip, the bump includes a plurality of much smaller pillars that interface with a corresponding plurality of openings in the insulating layer. In so doing, the low-k layer within the flip chip experiences much less stress and hence, fewer failures.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Applicant: Western Digital Technologies, Inc.Inventors: Shenghua HUANG, Yangming LIU, Bo YANG, Ning YE
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Publication number: 20230328910Abstract: A data storage device includes an enclosure and a Printed Circuit Board Assembly (PCBA) extending in a basal plane, and a plurality of semiconductor memory packages electromechanically bonded to the PCBA and coupled to the enclosure with thermal interface material. The data storage device further includes a first fitting coupled to a first end of the PCBA and the enclosure, restricting movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane. The data storage device further includes a second fitting coupled to a second end of the PCBA, allowing movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: Western Digital Technologies, Inc.Inventors: Bo Yang, Warren Middlekauff, Sean Lau, Ning Ye, Shrikar Bhagath, Yangming Liu
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Publication number: 20230170312Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and a reinforcing layer suspended within the molding compound. The reinforcing layer may for example be a copper foil formed in the molding compound over the semiconductor dies during the compression molding process. The reinforcing layer may have a structural rigidity which provides additional strength to the semiconductor device. The reinforcing layer may also be formed of a thermal conductor to draw heat away from a controller die within the semiconductor device.Type: ApplicationFiled: November 29, 2021Publication date: June 1, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yangming Liu, Shenghua Huang, Bo Yang, Ning Ye, Cong Zhang
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Publication number: 20230101826Abstract: A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.Type: ApplicationFiled: September 27, 2021Publication date: March 30, 2023Applicant: Western Digital Technologies, Inc.Inventors: Shenghua Huang, Yangming Liu, Bo Yang, Ning Ye
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Publication number: 20220406695Abstract: A semiconductor device package includes a semiconductor device with a ball grid array having a first subset of solder balls composed of metallic solder, and a second subset of solder balls composed of a composite material that includes a polymer core surrounded by a solder layer. The solder balls of the second subset can have a lower elastic modulus than the solder balls of the first subset and resist cracking due to thermal stresses on the semiconductor device package. In one embodiment, at least a portion of the second subset of solder balls is located on the periphery of the ball grid array such that the first subset of solder balls may be surrounded, at least partially, by the second subset of solder balls.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Applicant: Western Digital Technologies, Inc.Inventors: Siqi Zhang, Xu Wang, Wei Wang, Yangming Liu, Pradeep Rai
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Patent number: 11393735Abstract: A semiconductor device is disclosed having reinforced supports at corners of the device. The semiconductor device may include solder balls on a lower surface of the device for soldering the device onto a printed circuit board. In one example, the solder balls at the corners of the semiconductor device may be replaced by support billets having more mass and more contact area between the semiconductor device and the PCB. In a further example, screws may be provided at the corners of the device (instead of the corner solder balls or in addition to the corner solder balls). These screws may be placed through the corners of the semiconductor device and into the printed circuit board.Type: GrantFiled: February 15, 2019Date of Patent: July 19, 2022Assignee: Western Digital Technologies, Inc.Inventors: Yangming Liu, Ning Ye, Chin-Tien Chiu
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Patent number: 11177242Abstract: A semiconductor device is disclosed including one or more semiconductor dies mounted on substrate. Each semiconductor die may be formed with a ferromagnetic layer on a lower, inactive surface of the semiconductor die. The ferromagnetic layer pulls the semiconductor dies down against each other and the substrate during fabrication to prevent warping of the dies. The ferromagnetic layer also balances out a mismatch of coefficients of thermal expansion between layers of the dies, thus further preventing warping of the dies.Type: GrantFiled: March 10, 2020Date of Patent: November 16, 2021Assignee: Western Digital Technologies, Inc.Inventors: Yangming Liu, Ning Ye, Bo Yang
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Patent number: 11177239Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.Type: GrantFiled: March 8, 2018Date of Patent: November 16, 2021Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.Inventors: Shineng Ma, Chin-Tien Chiu, Chih-Chin Liao, Ye Bai, Yazhou Zhang, Yanwen Bai, Yangming Liu
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Publication number: 20200411477Abstract: A semiconductor device is disclosed including one or more semiconductor dies mounted on substrate. Each semiconductor die may be formed with a ferromagnetic layer on a lower, inactive surface of the semiconductor die. The ferromagnetic layer pulls the semiconductor dies down against each other and the substrate during fabrication to prevent warping of the dies. The ferromagnetic layer also balances out a mismatch of coefficients of thermal expansion between layers of the dies, thus further preventing warping of the dies.Type: ApplicationFiled: March 10, 2020Publication date: December 31, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yangming Liu, Ning Ye, Bo Yang
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Patent number: 10854573Abstract: A substrate semiconductor layer is attached to a carrier substrate through a sacrificial bonding material layer. A plurality of semiconductor dies included within continuous material layers are formed on a front side of the substrate semiconductor layer. Each of the continuous material layers continuously extends over areas of the plurality of semiconductor dies. A plurality of dicing channels is formed between neighboring pairs among the plurality of semiconductor dies by anisotropically etching portions of the continuous material layers located between neighboring pairs of semiconductor dies. The plurality of dicing channels extends to a top surface of the sacrificial bonding material layer. The sacrificial bonding material layer is removed selective to materials of surface portions of the plurality of semiconductor dies using an isotropic etch process. The plurality of semiconductor dies is singulated from one another upon removal of the sacrificial bonding material layer.Type: GrantFiled: January 16, 2019Date of Patent: December 1, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhongli Ji, Ning Ye, Tong Zhang, Hem Takiar, Yangming Liu
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Publication number: 20200219842Abstract: A substrate semiconductor layer is attached to a carrier substrate through a sacrificial bonding material layer. A plurality of semiconductor dies included within continuous material layers are formed on a front side of the substrate semiconductor layer. Each of the continuous material layers continuously extends over areas of the plurality of semiconductor dies. A plurality of dicing channels is formed between neighboring pairs among the plurality of semiconductor dies by anisotropically etching portions of the continuous material layers located between neighboring pairs of semiconductor dies. The plurality of dicing channels extends to a top surface of the sacrificial bonding material layer. The sacrificial bonding material layer is removed selective to materials of surface portions of the plurality of semiconductor dies using an isotropic etch process. The plurality of semiconductor dies is singulated from one another upon removal of the sacrificial bonding material layer.Type: ApplicationFiled: January 16, 2019Publication date: July 9, 2020Inventors: Zhongli Ji, Ning Ye, Tong Zhang, Hem Takiar, Yangming Liu
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Publication number: 20200006184Abstract: A semiconductor device is disclosed having reinforced supports at corners of the device. The semiconductor device may include solder balls on a lower surface of the device for soldering the device onto a printed circuit board. In one example, the solder balls at the corners of the semiconductor device may be replaced by support billets having more mass and more contact area between the semiconductor device and the PCB. In a further example, screws may be provided at the corners of the device (instead of the corner solder balls or in addition to the corner solder balls). These screws may be placed through the corners of the semiconductor device and into the printed circuit board.Type: ApplicationFiled: February 15, 2019Publication date: January 2, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yangming Liu, Ning Ye, Chin-Tien Chiu
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Patent number: 10236276Abstract: A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.Type: GrantFiled: June 12, 2017Date of Patent: March 19, 2019Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.Inventors: Yangming Liu, Chin-Tien Chiu, Zhongli Ji, Shaopeng Dong, Zengyu Zhou
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Publication number: 20190006320Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.Type: ApplicationFiled: March 8, 2018Publication date: January 3, 2019Applicant: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD.Inventors: Shineng Ma, Chin-Tien Chiu, Chih-Chin Liao, Ye Bai, Yazhou Zhang, Yanwen Bai, Yangming Liu
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Publication number: 20180294251Abstract: A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.Type: ApplicationFiled: June 12, 2017Publication date: October 11, 2018Applicant: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD.Inventors: Yangming Liu, Chin-Tien Chiu, Zhongli Ji, Shaopeng Dong, Zengyu Zhou