Abstract: A memory (400) returns all bit lines to a predetermined voltage level optimum for subsequent fast sensing. The memory (400) includes precharge circuitry (106, 108, 110) which begins the precharge operation during the latching phase of a prior access. The precharge circuitry (106, 108, 110) precharges all bit lines, rather than a selected bit line, to the predetermined voltage level prior to address decoding. In order to prevent "walk-up", the memory (400) includes circuitry such as a switched capacitor (138, 140) which draws current from the bit lines to reduce the voltage on a bit line which drove a logic high level in an earlier cycle or which had an increased voltage due to capacitive cross-coupling to an adjacent bit line. The memory (400) may also include devices such as transmission gates (142, 144, 146) to couple together adjacent bit lines and thereby more evenly distribute the precharging.

Abstract: A non-linear charge pump (1120) provides various voltages for use in a nonvolatile memory (400) and operates at low power supply voltages. The non-linear charge pump (1120) includes at least two non-linear voltage doubling stages (1132, 1134), which allows a capacitor formed with relatively thin gate oxide in a first stage (1132) to be made larger than a capacitor formed using relatively thick gate oxide in a second stage (1134). An output of a last voltage doubling stage (1136) is then input to a linear stage (1150) to generate a precise voltage. Another charge pump (1140) including non-linear stages (1142, 1144) followed by a linear stage (1146) is used to generate a reference voltage for the main non-linear charge pump (1130). The nonlinear stage (1130) includes a special bulk biasing circuit to bias the bulk of a transistor (1285) on the output side of the charging circuit (1284, 1285, 1286, 1287) continuously to prevent forward biasing the parasitic drain-bulk diode.