Abstract: A storage device comprises a nonvolatile memory configured to store data that is written in size units of a mapping size, and a storage controller configured to transmit a command to the nonvolatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapping size. The storage controller includes processing circuitry configured to transmit a read command to the nonvolatile memory, to cause the nonvolatile memory to read second data stored in the nonvolatile memory addressed based on the first address, in response to a determination that the first size is smaller than the mapping size and before the first data is received at the storage controller through the host interface.

Abstract: An open channel solid state drive includes a flash memory including a first block and a controller which controls the flash memory, the controller receiving write data and a physical address of the first block from a host and attempting a write of the data in the first block. The controller generates first data which is not written in the first block among the write data when a power-off occurs during writing attempt. The write data includes the first data and second data already written in the first block. The controller determines whether successive writing of the first data in the first block is possible or impossible. If the successive writing is possible, the controller successively writes the data in the first block. If the successive writing is impossible, the host or the controller writes the first data and the second data in a second block of the flash memory.

Abstract: A storage device includes a non-volatile memory; a plurality of cores; a host interface configured to receive a first set command, an I/O command, and an ADMIN command from a host; and a storage controller including a command distribution module configured to be set to a first state according to the first set command, and distribute the I/O command to the plurality of cores according to the set first state. Each of the plurality of cores may be configured to perform an operation instructed by the I/O command and an operation instructed by the ADMIN command on the non-volatile memory in response to the distributed I/O command.

Abstract: A storage device comprises a nonvolatile memory configured to store data that is written in size units of a mapping size, and a storage controller configured to transmit a command to the nonvolatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapping size. The storage controller includes processing circuitry configured to transmit a read command to the nonvolatile memory, to cause the nonvolatile memory to read second data stored in the nonvolatile memory addressed based on the first address, in response to a determination that the first size is smaller than the mapping size and before the first data is received at the storage controller through the host interface.

Abstract: A storage device includes a non-volatile memory; a plurality of cores; a host interface configured to receive a first set command, an I/O command, and an ADMIN command from a host; and a storage controller including a command distribution module configured to be set to a first state according to the first set command, and distribute the I/O command to the plurality of cores according to the set first state. Each of the plurality of cores may be configured to perform an operation instructed by the I/O command and an operation instructed by the ADMIN command on the non-volatile memory in response to the distributed I/O command.

Abstract: An open channel solid state drive includes a flash memory including a first block and a controller which controls the flash memory, the controller receiving write data and a physical address of the first block from a host and attempting a write of the data in the first block. The controller generates first data which is not written in the first block among the write data when a power-off occurs during writing attempt. The write data includes the first data and second data already written in the first block. The controller determines whether successive writing of the first data in the first block is possible or impossible. If the successive writing is possible, the controller successively writes the data in the first block. If the successive writing is impossible, the host or the controller writes the first data and the second data in a second block of the flash memory.

Abstract: An open channel solid state drive includes a flash memory including a first block and a controller which controls the flash memory, the controller receiving write data and a physical address of the first block from a host and attempting a write of the data in the first block. The controller generates first data which is not written in the first block among the write data when a power-off occurs during writing attempt. The write data includes the first data and second data already written in the first block. The controller determines whether successive writing of the first data in the first block is possible or impossible. If the successive writing is possible, the controller successively writes the data in the first block. If the successive writing is impossible, the host or the controller writes the first data and the second data in a second block of the flash memory.

Abstract: An open channel solid state drive includes a flash memory including a first block and a controller which controls the flash memory, the controller receiving write data and a physical address of the first block from a host and attempting a write of the data in the first block. The controller generates first data which is not written in the first block among the write data when a power-off occurs during writing attempt. The write data includes the first data and second data already written in the first block. The controller determines whether successive writing of the first data in the first block is possible or impossible. If the successive writing is possible, the controller successively writes the data in the first block. If the successive writing is impossible, the host or the controller writes the first data and the second data in a second block of the flash memory.

Abstract: A method for operating the 3D NAND device includes providing first and second dies and initial read levels for the first and second dies, changing the initial read level for the first die to a first read level based on a first offset that is calculated in consideration of elapsed time from a time point when a program for the first die is completed, changing the initial read level for the second die to a second read level based on a second offset that is calculated in consideration of elapsed time from a time point when a program for the second die is completed, and reading data stored in the first die using the first read level or reading data stored in the second die using the second read level.

Abstract: A swapping method performed using a data processing device, which includes a processor including a plurality of cores, the swapping method including searching for an empty page of a swap memory in response to the swap memory being connected to the data processing device, the search being performed by using at least one core of the plurality of cores, selecting a page to be swapped from a main memory of the data processing device, the selection being performed by using the at least one core by accessing a corresponding main memory list among a plurality of main memory lists, and swapping data of the page selected to be swapped to the empty page, the swapping being performed by using the at least one core.

Abstract: A memory device may include a normal cell which is configured to be programmed to a first resistance and stabilized as a resistance of the normal cell drifts from the first resistance to a second resistance; a flag cell which is configured to be programmed to a third resistance smaller than the first resistance and stabilized as a resistance of the flag cell drifts from the third resistance to a fourth resistance smaller than the second resistance; and a decision circuit which is configured to decide whether the flag cell has been stabilized in order to determine whether the normal cell has been stabilized.

Abstract: A swapping method performed using a data processing device, which includes a processor including a plurality of cores, the swapping method including searching for an empty page of a swap memory in response to the swap memory being connected to the data processing device, the search being performed by using at least one core of the plurality of cores, selecting a page to be swapped from a main memory of the data processing device, the selection being performed by using the at least one core by accessing a corresponding main memory list among a plurality of main memory lists, and swapping data of the page selected to be swapped to the empty page, the swapping being performed by using the at least one core.