Abstract: An architecture of radio frequency front-end includes a power amplifier module integrated duplexer (PAMiD), an antenna and at least one tunable matching network; herein, the PAMiD includes a power amplifier, and the at least one tunable matching network is located between the power amplifier and the antenna, and is configured to adjust the impedance of the output end of the power amplifier and/or the impedance of the input end of the antenna.

Abstract: An orthogonal signal generator includes a first stage phase shifting circuit and a second stage phase shifting circuit. The output end of the first stage phase shifting circuit is connected with the input end of the second stage phase shifting circuit, an impedance of the first stage phase shifting circuit is adjustable based on the frequency of a first input signal. The first stage phase shifting circuit is configured to phase-shift the first input signal by a first phase shifting angle to generate a first phase shifting angle signal. An impedance of the second stage phase shifting circuit is adjustable based on a frequency of a second input signal. The second stage phase shifting circuit is configured to phase-shift the phase-shifted second input signal by a second phase shifting angle to output an orthogonal signal with the corresponding frequency.

Abstract: An amplifier assembly includes an orthogonal signal generator, an adder and an amplification circuit. An output end of the orthogonal signal generator is connected with an input end of the adder, and the orthogonal signal generator is configured to generate an orthogonal signal. An output end of the adder is connected with an input end of the amplification circuit, and the adder is configured to vector-synthesize the orthogonal signal to output a first signal. The amplification circuit is configured to amplify a power of the first signal and compensate a phase of the first signal to output a second signal.

Abstract: A circuit for protecting a power amplifier includes a protection control circuit, an inter-stage adjustment circuit and a multi-stage power amplification circuit. The inter-stage adjustment circuit is connected in series between at least two adjacent power amplification circuits in the multi-stage power amplification circuit. The protection control circuit is configured to: control the inter-stage adjustment circuit to be in a turn-off state when overload protection of any stage power amplification circuit is enabled; and control the inter-stage adjustment circuit to be in a turn-on state, after a preset time elapses from the overload protection of the power amplification circuit being closed. In this way, damage of the power amplifier due to excessive input power may be avoided by the inter-stage adjustment circuit, thereby achieving a function of protecting the power amplifier.

Abstract: A protection circuit for the power amplifier includes a detection circuit, a controller and an input impedance adjustment circuit. The detection circuit is provided with an input end connected to the power amplifier and an output end connected to an input end of the controller, and is configured to detect an operation electrical signal of the power amplifier and generate a trigger electrical signal. The controller is configured to generate a first control signal and a second control signal, the first control signal is configured to control a bias current or bias voltage of the power amplifier to reduce or recover a gain of the power amplifier, and the second control signal is configured to adjust characteristic parameters of the input impedance adjustment circuit. The input impedance adjustment circuit is configured to decrease or increase input power of the power amplifier in response to the second control signal.

Abstract: A circuit for protecting an amplifier includes a detection circuit, a controller and a bypass impedance adjustment circuit. The detection circuit is configured to detect an operation electrical signal of a power amplifier and generate a trigger electrical signal based on the operation electrical signal correspondingly. A first output end of the controller is connected to a base or a gate or a bias circuit of the power amplifier, and a second output end of the controller is connected to a control input end of the bypass impedance adjustment circuit. The bypass impedance adjustment circuit is connected in parallel with the power amplifier. The controller is configured to generate a first control signal and a second control signal based on the trigger electrical signal, and the first control signal is configured to control a bias current or bias voltage of the power amplifier.

Abstract: An architecture of radio frequency front-end includes a power amplifier module (PAM), a front-end module integrated duplexer (FEMiD), an antenna and at least one tunable matching network. The PAM includes a power amplifier, and the at least one tunable matching network is located between the power amplifier and the antenna and is configured to adjust at least one of the impedance of the output end of the power amplifier or the impedance of the input end of the antenna.

Abstract: An architecture of radio frequency front-end includes a power amplifier module (PAM), a front-end module integrated duplexer (FEMiD), an antenna and at least one tunable matching network. The PAM includes a power amplifier, and the at least one tunable matching network is located between the power amplifier and the antenna and is configured to adjust at least one of the impedance of the output end of the power amplifier or the impedance of the input end of the antenna.

Abstract: An architecture of radio frequency front-end includes a power amplifier module integrated duplexer (PAMiD), an antenna and at least one tunable matching network; herein, the PAMiD includes a power amplifier, and the at least one tunable matching network is located between the power amplifier and the antenna, and is configured to adjust the impedance of the output end of the power amplifier and/or the impedance of the input end of the antenna.