Patents by Inventor Yangyang Sun

Yangyang Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12660649
    Abstract: A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: June 16, 2026
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yangyang Sun, Srikanth Kulkarni, Lily Zhao, Milind Shah
  • Publication number: 20260153405
    Abstract: The present disclosure relates to metrology measurement systems and related methods. In one or more embodiments a measurement system is provided. The measurement system includes a stage operable to retain an object and a light engine disposed above the stage. The light engine includes a light source directed towards the object, a first lens operable to collimate or focus a light from the light source, a reticle tray disposed between the light source and the first lens, and a reticle coupled to a reticle tray. The reticle includes a pattern and an anti-reflective coating disposed on the reticle. The coating is aligned with the pattern.
    Type: Application
    Filed: October 27, 2023
    Publication date: June 4, 2026
    Inventors: Yongan XU, Yangyang SUN, Jinxin FU
  • Publication number: 20260150664
    Abstract: A package comprising an integrated device and a substrate coupled to the integrated device through a plurality of solder interconnects. The integrated device comprises a die substrate; a die interconnection portion coupled to the die substrate; a plurality of pad interconnects coupled to the die interconnection portion; a plurality of pillar interconnects coupled to the plurality of pad interconnects; and a plurality of interconnects coupled to the plurality of pillar interconnects, wherein at least one pad interconnect from the plurality of pad interconnects, at least one pillar interconnects from the plurality of pillar interconnects and at least one interconnect from the plurality of interconnects are configured as an inductor.
    Type: Application
    Filed: November 22, 2024
    Publication date: May 28, 2026
    Inventors: Hsiao-Tsung YEN, Yangyang SUN, Yujen CHEN
  • Publication number: 20260106668
    Abstract: The present disclosure describes a metrology system. The system includes a an optical source, a first sensor, and a second sensor. The optical source is positioned on a first side of an optical device held by a stage. The first sensor is positioned on the first side of the optical device. During a first mode, the first sensor detects a first optical signal from the optical source reflected from the optical device. During a second mode, the second sensor moves such that (i) the second sensor is positioned on a second side of the optical device opposite the first side of the optical device and (ii) the second sensor detects a second optical signal from the optical source transmitted through the optical device.
    Type: Application
    Filed: September 26, 2025
    Publication date: April 16, 2026
    Inventors: Haoran WANG, Jinxin FU, Daihua ZHANG, Yangyang SUN, Ludovic GODET
  • Patent number: 12603377
    Abstract: A protective cover may comprise: a first cover configured to be fixed to a frame of a battery, the first cover being provided with an accommodating cavity for accommodating a high-voltage lead-out structure, and the accommodating cavity having an opening for exposing the high-voltage lead-out structure; a second cover rotatably arranged on the first cover and opening and respectively closing the opening when rotated relative to the first cover in a first direction of rotation and a second direction of rotation; and a cover closing structure connected to the first cover and the second cover, and causing the second cover to rotate in the second direction of rotation after the second cover is opened and an external force for opening the second cover is removed.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: April 14, 2026
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY (HONG KONG) LIMITED
    Inventors: Hongqi Wang, Yangyang Sun, Bo Wu, Jianhua Liu
  • Publication number: 20260101805
    Abstract: A package comprising a first integrated device; a second integrated device coupled to the first integrated device through an adhesive; a first plurality of wire bonds coupled to the first integrated device; a second plurality of wire bonds coupled to the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, the first plurality of wire bonds and the second plurality of wire bonds; and a plurality of pillar interconnects.
    Type: Application
    Filed: September 20, 2024
    Publication date: April 9, 2026
    Inventors: Yangyang SUN, Lily ZHAO, Periannan CHIDAMBARAM, Zhongze WANG, Jihong CHOI, Yujen CHEN
  • Patent number: 12560510
    Abstract: The present disclosure relates to metrology measurement systems, and related methods. In one or more embodiments a system, includes a substrate support, and an optical arm. The optical arm includes a light source operable to project a first beam on a first light path. The optical arm also includes a first lens, a first beam splitter, a second lens, a first detector, and an aperture. The first lens is disposed on the first light path and between the substrate support and the light source. The first beam splitter is disposed on the first light path. The first beam splitter is positioned between the substrate support and the light source. The first detector is disposed on the second light path. The second lens focuses the second beam to a second beam diameter. The aperture is disposed between the second lens and the first detector.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: February 24, 2026
    Assignee: Applied Materials, Inc.
    Inventors: Yangyang Sun, Jinxin Fu, Ravi Komanduri, Chi-Yuan Yang
  • Publication number: 20260050166
    Abstract: Embodiments of the present disclosure generally relate to augmented reality systems. More specifically, embodiments described herein provide for augmented reality systems, methods of correcting an image projected into a waveguide, and related components. In one or more embodiments, an augmented reality system includes a light engine configured to emit an image and a waveguide including a substrate. The waveguide further includes an input coupler disposed over the substrate and configured to receive the image from the light engine. An output coupler is disposed over the substrate and configured to emit an outcoupled image. A controller is configured to generate corrective data based on one or more characteristics of the outcoupled image and adjust one or more components of the augmented reality system based on the corrective data.
    Type: Application
    Filed: August 18, 2025
    Publication date: February 19, 2026
    Inventors: Yi XU, Deming Meng, Yangyang SUN, Jinxin FU
  • Publication number: 20260033319
    Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The integrated device comprises a die substrate; and a plurality of pillar interconnects comprising a first plurality of pillar interconnects, wherein at least one pillar interconnect from the first plurality of pillar interconnects comprises a planar cross sectional shape that includes a concave portion.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 29, 2026
    Inventors: Aniket PATIL, Yujen CHEN, Yangyang SUN
  • Publication number: 20260018548
    Abstract: Various aspects of the present disclosure generally relate to integrated circuit devices, and to a conductive structure with multiple support pillars. A device includes a die including a contact pad. The device also includes a conductive structure. The conductive structure includes multiple support pillars coupled to the die, a bridge coupled to each of the multiple support pillars, and a cap pillar coupled to the bridge opposite the multiple support pillars. The device further includes a solder cap coupled to the cap pillar. The solder cap is electrically connected to the contact pad via the cap pillar, the bridge, and at least one of the multiple support pillars.
    Type: Application
    Filed: July 9, 2024
    Publication date: January 15, 2026
    Inventors: Yujen CHEN, Aniket PATIL, Yangyang SUN
  • Patent number: 12525574
    Abstract: A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 13, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Yangyang Sun, Stanley Seungchul Song, Lily Zhao
  • Patent number: 12500187
    Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate; an interconnection die coupled to the first substrate; a second substrate coupled to the first substrate through the interconnection die such that the first integrated device and the interconnection die are located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: December 16, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yangyang Sun, Zhijie Wang, Wei Wang, Marcus Hsu
  • Patent number: 12500188
    Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: December 16, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dongming He, Jun Chen, Yangyang Sun, Lily Zhao, Ahmer Syed
  • Publication number: 20250377484
    Abstract: Embodiments of the present disclosure relate to a sensor apparatuses with stacked metasurfaces suitable for small form factors. The apparatus is a sensing apparatus operable to be used in sensing applications. The apparatus includes a light source and an optical device. The optical device includes multiple metasurfaces. The optical device includes a collimation metasurface disposed on a substrate to collimate one or more laser beams from the light source. The one or more laser beams propagate through the substrate to a diffractive metasurface. The diffractive metasurface diffracts the collimated one or more laser beams into diffraction beams.
    Type: Application
    Filed: August 21, 2025
    Publication date: December 11, 2025
    Inventors: Jinxin FU, Yangyang SUN, Ludovic GODET
  • Publication number: 20250357288
    Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; an underfill located between the first integrated device and the substrate; and a back side interconnect located over the underfill and a back side of the first integrated device.
    Type: Application
    Filed: May 14, 2024
    Publication date: November 20, 2025
    Inventors: Aniket PATIL, Yujen CHEN, Yangyang SUN
  • Patent number: 12469811
    Abstract: A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: November 11, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yangyang Sun, Rong Zhou, Li-Sheng Weng, Lily Zhao
  • Patent number: 12463127
    Abstract: Integrated circuit (IC) packages employing a re-distribution layer (RDL) substrate(s) with photosensitive non-polymer dielectric material layers for increased package rigidity, and related fabrication methods. To reduce or minimize warpage of an IC package employing a RDL substrate, the RDLs of the RDL substrate are photosensitive non-polymer dielectric material layers. The photosensitive non-polymer dielectric material layers can exhibit increased rigidity as a result of being hardened when exposed to light and cured during fabrication of the RDL substrate. The photosensitive non-polymer dielectric material layers can also exhibit increased rigidity as a result of being an inorganic polymer (e.g., SiOx, SiN material) that has a higher material modulus for increased stiffness and/or a lower coefficient of thermal expansion (CTE) for reduced thermal contraction and expansion, as opposed to for example, an organic polymer material (e.g., Polyimide) which has less stiffness and a higher CTE.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: November 4, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yangyang Sun, Manuel Aldrete, Wei Wang
  • Publication number: 20250309078
    Abstract: A semiconductor die having a die interconnect and a die level distribution (DLD) metallization layer having a metal line and a metal pad having a width greater than the width of the metal line to support a larger die interconnect for improved signal path conductivity between the die interconnect and the metal pad is disclosed. Related integrated circuit (IC) packages and fabrication methods are also disclosed. The die includes a semiconductor layer, a DLD metallization structure, and a back end of line (BEOL) interconnect structure between the semiconductor layer and the DLD metallization structure. The DLD metallization structure mechanically supports die interconnects for coupling the die to another device, such as a package substrate or another die, and redistributes signals (e.g., power, ground, information) between the die interconnects and the semiconductor layer through the BEOL interconnect structure.
    Type: Application
    Filed: April 1, 2024
    Publication date: October 2, 2025
    Inventors: Yangyang Sun, Wei Hu, Dongming He, Lily Zhao
  • Publication number: 20250300133
    Abstract: Disclosed are stacked packages in which through-mold cavities are formed within the mold and filled with thermally conductive pillars. The pillars are thermally coupled to a die. In this way, the heat from the die can be conducted away.
    Type: Application
    Filed: March 19, 2024
    Publication date: September 25, 2025
    Inventors: Yujen CHEN, Yangyang SUN
  • Publication number: 20250300104
    Abstract: An integrated device comprising a die substrate; a die interconnection coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnection; a plurality of pad interconnects coupled to the die interconnection; a passivation layer coupled to the die interconnection; and a plurality of metallization interconnects, wherein one or more metallization interconnects from the plurality of metallization interconnects is coupled to one or more pad interconnects from the plurality of pad interconnects, wherein the plurality of metallization interconnects comprise a first step pad interconnect structure.
    Type: Application
    Filed: March 20, 2024
    Publication date: September 25, 2025
    Inventors: Yangyang SUN, Xuefeng ZHANG, Jun CHEN