Abstract: A device comprising an integrated device. The integrated device comprising a die substrate; an interconnect portion coupled to the die substrate, a plurality of pillar interconnects and a passivation layer coupled to the interconnect portion. The interconnect portion includes a first plurality of pads and a second plurality of pads. The first plurality of pads are configured to provide a first plurality of electrical paths for input/output signals. The second plurality of pads are configured to provide a second plurality of electrical paths for power. The plurality of pillar interconnects are coupled to the first plurality of pads and the second plurality of pads. The passivation layer comprises a plurality of openings. The plurality of openings include at least one opening located over a pad from the first plurality of pads.

Abstract: A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

Abstract: Measurement systems and methods of optical device metrology as described herein. In an example, a method includes projecting a light beam of a first intensity to a lens coupler disposed on a first surface of an optical device substrate, the lens coupler in-coupling the light beam into the optical device substrate to undergo total internal refraction. The optical device substrate includes a grating having a plurality of grating lines such that light is out-coupled by the grating at a plurality of contact points. A plurality of intensities of the light beam out-coupled by the grating at the plurality of contact points are measured using a receiver and a total optical loss of the optical device substrate and the grating are determined by comparing the plurality of intensities at the contact points and the first intensity of the light beam.

Abstract: Disclosed are deep trench capacitors (DTC), also referred to as multi-terminal caps. In conventional DTCs, a plurality of conductive bumps are formed on a base, in which alternating bumps are coupled to power and ground. It is proposed to increase the increase the bump density by providing one or more concentric bump structures in which at least one bump structure includes an inner bump and an outer bump surrounding the inner bump with an insulator in between. The inner bump may be coupled to a first voltage (e.g., power) and the outer bump may be coupled to a second voltage (e.g., ground).

Abstract: A package comprising a metallization portion comprising at least one dielectric layer; and a plurality of metallization interconnects; a bridge comprising a bridge alignment structure, wherein the bridge is located at least partially in the metallization portion; a first integrated device coupled to the bridge and the metallization portion; and a second integrated device coupled to the bridge and the metallization portion.

Abstract: A package comprising a substrate comprising at least one dielectric layer; and a plurality of interconnects comprising: a first plurality of landing pad interconnects, wherein at least one landing pad interconnect from the first plurality of landing pad interconnects has an elongated planar shape; and a second plurality of landing pad interconnects, wherein at least one landing pad interconnect from the second plurality of landing pad interconnects has an elongated planar shape; and an integrated device coupled to the first plurality of landing pad interconnects and the second plurality of landing pad interconnects.

Abstract: A package comprising a substrate comprising: at least one dielectric layer; and a plurality of interconnects comprising a stack of interconnects that include a first pad interconnect; a first via interconnect coupled to the first pad interconnect; a second pad interconnect coupled to the first via interconnect; at least two second via interconnect coupled to the second pad interconnect; and a third pad interconnect coupled to the at least two second via interconnect; and an integrated device coupled to the stack of interconnects.

Abstract: A die includes a plurality of pillar bumps configured to electrically connect the die to a substrate. The plurality of pillar bumps includes at least one first pillar bump having a first total pillar bump height. The at least one first pillar bump includes a first pillar having a first pillar height and a first solder cap having a first solder cap height. The plurality of pillar bumps includes at least one second pillar bump having a second pillar height substantially equal to the first total pillar bump height. The at least one second pillar bump includes a second pillar having a second pillar height and a second solder cap having a second solder cap height. The second pillar height is greater than the first pillar height, and the second solder cap height is less than the first solder cap height.

Abstract: In an aspect, a substrate structure includes plurality of substrates encapsulated in a shell in a stacked relationship; at least one electronic component in each substrate of the plurality of substrates, wherein the at least one electronic component includes at least a first terminal and a second terminal; a first redistribution layer (RDL) disposed over each substrate of the plurality of substrates configured to electrically couple the first terminal of the at least one electronic component with a respective first terminal disposed over an outer edge of the shell; and a second RDL disposed over each substrate of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component with a respective second terminal disposed over the outer edge of the shell.

Abstract: Provided are a battery module end plate, a battery module, and a preparation method for a battery module end plate. The preparation method includes: providing a first blank and stamping the first blank to obtain a first plate body; providing a molding die and placing the first plate body into the molding die; providing a second blank and melting the second blank to obtain a molten material; and injecting the molten material into the molding die to allow the molten material to be wrapped around the first plate body, and obtaining the battery module end plate through cooling. The battery module end plate includes the first plate body and a second plate body formed by cooling the molten material and wrapped around the first plate body.

Abstract: A stacked IC device includes a first memory die and a second memory die coupled to the substrate. The stacked IC device also includes a logic die electrically connected, face-to-face, to the first memory die and the second memory die and electrically connected to the substrate by conductors that extend through a region between the first memory die and the second memory die.

Abstract: Embodiments described herein provide for light engines of a measurement system and methods of using the light engines. The measurement system includes a light engine operable to illuminate a first grating of an optical device. The light engine projects a pattern with a light from a light engine. The light engine projects a pattern to the first grating such that a metrology metric may be extracted from one or more images captured by a detector of the measurement system. The metrology metrics are extracted by processing the image. The metrology metrics determine if the optical device meets image quality standards.

Abstract: Embodiments herein provide for a measurement system for determining an optical device modulation transfer function (MTF). The measurement system includes a stage operable to retain an optical device or an optical device substrate having at least one optical device disposed thereon. A light engine is disposed above the stage. The light engine includes a light source operable to project a light to the optical device at a range of wavelengths. A reticle is operable to form a pattern from the light projected from the light source. A first lens operable to collimate the light from the light source toward the optical device or optical device substrate. A near field detector is operable to detect the light from the optical device or optical device substrate. A far field detector is operable to detect the light from the optical device of optical device substrate.

Abstract: A device includes a plurality of contacts on a first side. The device also includes first interconnect conductors along a first edge of the die, and second interconnect conductors external to the die and along a second edge of the die. The device further includes redistribution layers coupled to a second side of the die, where the redistribution layers define a plurality of pairs of conductive paths between the first interconnect conductors and the second interconnect conductors.

Abstract: A device includes a first die and a second die. The first die includes a first set of external contacts on a first side of the first die, a first plurality of through-substrate vias (TSVs) that extend between the first side of the first die and a second side of the first die, and interface or control circuitry proximate to the first side of the first die. The second die includes a second set of external contacts on a first side of the second die, a second plurality of TSVs that extend between the first side of the second die and a second side of the second die, and processor circuitry proximate to the first side of the second die and configured to access an external resource via the interface or control circuitry.

Abstract: Aspects disclosed an integrated circuit (IC) package having a mold layer between a die and a substrate comprising two types of resin to improve die interconnects having different sizes. The die interconnects include a first set of die interconnects and a second set of die interconnects. The first set of die interconnects are smaller and have a tighter pitch than the second set of die interconnects. A first resin is disposed around each of the first set of die interconnects. A second resin is disposed around each of the second set of die interconnects. These two types of resin enable a die to deploy die interconnects with different sizes which can increase the number of the first set of die interconnects and improve the power transfer over the second set of die interconnects.

Abstract: An integrated device comprising a die portion that includes a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, where the plurality of under bump metallization interconnects comprises a first under bump metallization interconnect. The integrated device includes a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, where the plurality of pillar interconnects includes a first pillar interconnect. The first pillar interconnect includes a first width that corresponds to a widest part of the first pillar interconnect, and a second width that corresponds to a part of the first pillar interconnect that is vertically farthest away from the first under bump metallization interconnect, wherein the second width is less than the first width.

Abstract: A package comprising a metallization portion; a first integrated device coupled to the metallization; a second integrated device coupled to the first integrated device through an adhesive; a first plurality of wire bonds coupled to the second integrated device and the metallization portion; and an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device and the first plurality of wire bonds.

Abstract: A package includes a first die, a second die, and a third die. The first die includes first active circuitry, and a first plurality of conductive vias (CVs) that has a first pitch. The second die includes second active circuitry proximate to a first side of the second die. The second active circuitry includes metal layers and a second plurality of CVs that extends from a second side of the second die to one or more of the metal layers. The second plurality of CVs has a second pitch greater than the first pitch. The third die includes a third plurality of CVs to electrically couple the second active circuitry to a substrate. The third plurality of CVs has a third pitch greater than the first pitch. The second die is disposed between the first die and the third die.

Abstract: A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.