Abstract: A class of pyrimidoheterocyclic compounds, and specifically disclosed is a compound represented by formula (III) or a pharmaceutically acceptable salt thereof.

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

Abstract: Disclosed is a composition for inhibiting nitrate decomposition and its preparation method, which belongs to a field of photocatalytic technology, comprising: weighing titanium dioxide and pure phase metal carbonate or pure phase metal bicarbonate proportionally; adding the weighed pure phase metal carbonate or the pure phase metal bicarbonate to titanium dioxide for grinding to obtain a metal carbonate/bicarbonate-containing mixture. The method of inhibiting nitrate decomposition using the metal carbonate/bicarbonate of the present disclosure has a significant ability to inhibit nitrate decomposition, and the experimental results show that the method of inhibiting nitrate decomposition using the metal carbonate/bicarbonate can effectively inhibit the decomposition of the nitrate under irradiation for a long time.

Abstract: Circuit packages with a polymer layer around the bump interconnects have a reduced number of shorts between the bump interconnects and have reduced underfill delamination. The circuit package includes a first component coupled to a second component through a plurality of bump interconnects employed for passing logic signals, data signals, and/or power. The bump interconnects extend from a surface of the first component and are coupled to contact pads on an opposing surface of the second component. The side surfaces of the bump interconnects extend in a direction from the second component to the first. The circuit package includes the polymer layer disposed on the surface of the first component around the bump interconnects and on the side surfaces of the bump interconnects. The polymer layer reduces shorts between the side surfaces of adjacent bump interconnects and reduces delamination of an underfill disposed between the first and second components.

Abstract: Embodiments of this application provide a composite structure including a substrate layer and a functional layer disposed on a surface of at least one side of the substrate layer. The substrate layer includes a first support member and a second support member that are disposed side by side and a bendable connecting member connected to and disposed between the first support member and the second support member. A material of the first support member and the second support member includes a hard rubber fiber composite material, and the functional layer includes one or more of an electrically conductive layer, a thermally conductive layer, or an impact-resistant layer.

Abstract: Embodiments described herein provide for devices and methods of measuring a pitch P of optical device structures and an orientation angle ? of the optical device structures. One embodiment of the system includes an optical arm coupled to an arm actuator. The optical arm includes a light source. The light source emits a light path operable to be diffracted to the stage. The optical arm further includes a first beam splitter and a second beam splitter positioned in the light path. The first beam splitter directs the light path through a first lens and the second beam splitter directs the light path through a first dove prism and a second lens. The optical arm further includes a first detector operable to detect the light path from the first lens and second detector operable to detect the light path from the second lens.

Abstract: Disclosed are techniques for selectively boosting conductive pillar bumps. In an aspect, an apparatus includes a plurality of metal pads, a first set of boosting pads attached to a first set of the plurality of metal pads, a first set of conductive pillar bumps attached to the first set of boosting pads, a second set of conductive pillar bumps attached to a second set of the plurality of metal pads, wherein heights of the first set of conductive pillar bumps are shorter than heights of the second set of conductive pillar bumps, and wherein heights of the first set of boosting pads plus the heights of the first set of conductive pillar bumps are within a tolerance threshold of the heights of the second set of conductive pillar bumps, and solder attached to the first set of conductive pillar bumps and the second set of conductive pillar bumps.

Abstract: An integrated device comprising a die portion that includes a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, where the plurality of under bump metallization interconnects comprises a first under bump metallization interconnect. The integrated device includes a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, where the plurality of pillar interconnects includes a first pillar interconnect. The first pillar interconnect includes a first width that corresponds to a widest part of the first pillar interconnect, and a second width that corresponds to a part of the first pillar interconnect that is vertically farthest away from the first under bump metallization interconnect, wherein the second width is less than the first width.

Abstract: Disclosed are integrated circuit structures with interconnects of small size, also referred to micro-bumps. As pitches of micro-bumps become smaller, their sizes also become small. This makes it difficult to probe the integrated circuit structure to verify their operations. To enable probing, test pads of larger pitches are provided. The test pads, usually formed of metal, may be protected with solder caps.

Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate; an interconnection die coupled to the first substrate; a second substrate coupled to the first substrate through the interconnection die such that the first integrated device and the interconnection die are located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate.

Abstract: A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.

Abstract: A package comprising a first metallization portion, a first integrated device, an interconnection die, a second metallization portion, and an encapsulation layer. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The first integrated device is coupled to the first metallization portion. The interconnection die is coupled to the first metallization portion. The second metallization portion coupled to the first metallization portion through the interconnection die such that the first integrated device and the interconnection die are located between the first metallization portion and the second metallization portion. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects.

Abstract: An ion chromatography (IC) suppressor includes a first clamping plate, an intermediate plate, a second clamping plate, a first ion exchange membrane, a second ion exchange membrane, a first electrode and a second electrode. The first clamping plate, the intermediate plate and the second clamping plate are tightly buckled in sequence to compact the first ion exchange membrane between the first clamping plate and the intermediate plate and compact the second ion exchange membrane between the intermediate plate and the second clamping plate. Resin particles are filled between the two ion exchange membranes. An eluent inlet and an eluent outlet are provided respectively at two ends of the intermediate plate, and an accommodating groove is formed at each of a tail end of the eluent inlet and a head end of the eluent outlet. The first clamping plate and the second clamping plate are provided with a sealing lip, respectively.

Abstract: Embodiments described herein provide for a measurement system having an aperture filtering component and methods of utilizing the measurement system. The measurement system described herein includes a measurement arm and a stage. The measurement arm projects a light beam to a top surface of an optical device structure. Multi-reflection beams resulting from reflections and diffraction off other surfaces of a non-opaque substrate leads to interference. The measurement arm includes an aperture (e.g., an aperture filtering component) that filters the multi-reflection beams from being relayed to the detector. As such, only images of the light beam are relayed to the detector.

Abstract: A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

Abstract: Embodiments of the present disclosure relate to optical devices for augmented, virtual, and/or mixed reality applications. In one or more embodiments, an optical device metrology system is configured to measure a plurality of see-through metrics for optical devices.

Abstract: Embodiments described herein relate to an optical device metrology system including a light source to emit a light and a non-polarizing beam splitter to split the light into a first photodetector light path and an optical light path. A first photodetector is disposed in the first photodetector light path and measures a total power of the light. The optical device substrate is disposed in the optical light path and splits the light into a second and a third photodetector light path. A second photodetector is disposed in the second photodetector light path from the optical device substrate. The second photodetector measures a reflected power of the light. A third photodetector is disposed in the third photodetector light path. The third photodetector measures a transmitted power of the light. The controller receives measurements from the first, second, and third photodetectors to calculate a percentage light loss within the optical device substrate.

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

Abstract: A protective cover may comprise: a first cover configured to be fixed to a frame of a battery, the first cover being provided with an accommodating cavity for accommodating a high-voltage lead-out structure, and the accommodating cavity having an opening for exposing the high-voltage lead-out structure; a second cover rotatably arranged on the first cover and opening and respectively closing the opening when rotated relative to the first cover in a first direction of rotation and a second direction of rotation; and a cover closing structure connected to the first cover and the second cover, and causing the second cover to rotate in the second direction of rotation after the second cover is opened and an external force for opening the second cover is removed.