Abstract: A multi-addend adder circuit used for multi-addend addition in a polar representation in stochastic computing. The multi-addend adder circuit includes a buffer circuit and a computing circuit, where the buffer circuit is configured to store to-be-buffered data for at least one cycle and output buffer data, and the computing circuit is configured to process a plurality of pieces of bitstream data and the buffer data and output one piece of bitstream data and the to-be-buffered data, where the piece of output bitstream data is a quotient of dividing a sum of summation data and the buffer data by a scale-down coefficient, the output to-be-buffered data is a remainder of dividing a sum of all summation data until a current cycle by the scale-down coefficient, and the summation data is a quantity of bits whose values are 1 in the plurality of pieces of first bitstream data.

Abstract: A voltage regulation circuit includes a first comparison and control unit and a second comparison and control unit. The first comparison and control unit is connected to a first switch unit, determine a first bias voltage based on a first output voltage, a first reference voltage, and a second reference voltage, and control a value of an equivalent resistance of the first switch unit using the first bias voltage. The second comparison and control unit is connected to a third switch unit and the second switch unit, determine a second bias voltage based on the first output voltage, a second output voltage, and a third reference voltage, and control values of equivalent resistances of the third switch unit and the second switch unit using the second bias voltage.

Abstract: A voltage regulation circuit includes a first comparison and control unit and a second comparison and control unit. The first comparison and control unit is connected to a first switch unit, determine a first bias voltage based on a first output voltage, a first reference voltage, and a second reference voltage, and control a value of an equivalent resistance of the first switch unit using the first bias voltage. The second comparison and control unit is connected to a third switch unit and the second switch unit, determine a second bias voltage based on the first output voltage, a second output voltage, and a third reference voltage, and control values of equivalent resistances of the third switch unit and the second switch unit using the second bias voltage.

Abstract: A voltage regulation circuit includes a first comparison and control unit and a second comparison and control unit. The first comparison and control unit is connected to a first switch unit, determine a first bias voltage based on a first output voltage, a first reference voltage, and a second reference voltage, and control a value of an equivalent resistance of the first switch unit using the first bias voltage. The second comparison and control unit is connected to a third switch unit and the second switch unit, determine a second bias voltage based on the first output voltage, a second output voltage, and a third reference voltage, and control values of equivalent resistances of the third switch unit and the second switch unit using the second bias voltage.

Abstract: A multi-addend adder circuit used for multi-addend addition in a polar representation in stochastic computing. The multi-addend adder circuit includes a buffer circuit and a computing circuit, where the buffer circuit is configured to store to-be-buffered data for at least one cycle and output buffer data, and the computing circuit is configured to process a plurality of pieces of bitstream data and the buffer data and output one piece of bitstream data and the to-be-buffered data, where the piece of output bitstream data is a quotient of dividing a sum of summation data and the buffer data by a scale-down coefficient, the output to-be-buffered data is a remainder of dividing a sum of all summation data until a current cycle by the scale-down coefficient, and the summation data is a quantity of bits whose values are 1 in the plurality of pieces of first bitstream data.

Abstract: A battery includes a housing, an electrical energy storage unit mounted inside the housing, and a battery control system electrically coupled to the electrical energy storage unit to control charge and discharge of the electrical energy storage unit. The battery control system includes one or more processors configured to obtain one or more electrical parameters of the battery in a storage state, determine whether the battery is damaged or abnormal according to the one or more electrical parameters of the battery, and automatically discharge the battery to a safe state in response to determining that the battery is damaged or abnormal.

Abstract: A voltage regulation circuit includes a first comparison and control unit and a second comparison and control unit. The first comparison and control unit is connected to a first switch unit, determine a first bias voltage based on a first output voltage, a first reference voltage, and a second reference voltage, and control a value of an equivalent resistance of the first switch unit using the first bias voltage. The second comparison and control unit is connected to a third switch unit and the second switch unit, determine a second bias voltage based on the first output voltage, a second output voltage, and a third reference voltage, and control values of equivalent resistances of the third switch unit and the second switch unit using the second bias voltage.

Abstract: A voltage regulation circuit includes an obtainer that is configured to obtain load information of a corresponding load and output the load information to a corresponding controller. The corresponding controller generates a switch control signal based on the load information and outputs the switch controller to at least one switch. The at least one switch regulates, based on the accurate switch control signal, a voltage input to the corresponding load.

Abstract: A voltage regulation method, a controller, and a chip are provided. In the method, a controller receives a digital first status representation value sent by a sensor; the controller determines, according to the first status representation value and at least one of a second status representation value or a first expected value, whether to regulate the supply voltage of the load, where the second status representation value represents a node voltage that is at a previous moment and that is of the detection point of the load, and the first expected value represents an expected value of a node voltage of the detection point; and when determining to regulate the supply voltage of the load, the controller sends a digital control signal to a power gating array, to control the power gating array to regulate the supply voltage.

Abstract: A differential input amplification-stage circuit comprises a voltage unit, first and second bulk-driven transistors, first and second mirror current sources, and a differential amplifier unit. The first and the second bulk-driven transistors respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents. The differential amplifier unit separately outputs first and second adjustment currents under an action of voltages output by the first to the third voltage output ends. The first and the second mirror current sources respectively output first and second predetermined currents according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit. Therefore, output stability is improved.

Abstract: A voltage regulation method, a controller, and a chip are provided. In the method, a controller receives a digital first status representation value sent by a sensor; the controller determines, according to the first status representation value and at least one of a second status representation value or a first expected value, whether to regulate the supply voltage of the load, where the second status representation value represents a node voltage that is at a previous moment and that is of the detection point of the load, and the first expected value represents an expected value of a node voltage of the detection point; and when determining to regulate the supply voltage of the load, the controller sends a digital control signal to a power gating array, to control the power gating array to regulate the supply voltage.

Abstract: A differential input amplification-stage circuit comprises a voltage unit, first and second bulk-driven transistors, first and second mirror current sources, and a differential amplifier unit. The first and the second bulk-driven transistors respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents. The differential amplifier unit separately outputs first and second adjustment currents under an action of voltages output by the first to the third voltage output ends. The first and the second mirror current sources respectively output first and second predetermined currents according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit. Therefore, output stability is improved.

Abstract: The present invention relates to a voltage regulator and a resonant gate driver of the voltage regulator, where the resonant gate driver is configured to drive a first power transistor and a second power transistor and includes: a first control gateway, a second control gateway, and an inductor, where: a first end of the first control gateway is connected to a first end of the second control gateway; a second end of the first control gateway is connected to a second end of the second control gateway by using the inductor; and a third end of the first control gateway is connected to the first power transistor, and a third end of the second control gateway is connected to the second power transistor. The resonant gate driver according to an embodiment of the present invention can reduce a driving period and increase a response speed.

Abstract: A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 . . . , I2k-1, and I2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1, . . . , Ok-2, and Ok-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O0=I0 if I0=I1, and O0=I2 otherwise; and when k>1, set Ok-1=I2k-1 if Ok-2=I2k-1, and Ok-1=I2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.

Abstract: The present invention relates to a voltage regulator and a resonant gate driver of the voltage regulator, where the resonant gate driver is configured to drive a first power transistor and a second power transistor and includes: a first control gateway, a second control gateway, and an inductor, where: a first end of the first control gateway is connected to a first end of the second control gateway; a second end of the first control gateway is connected to a second end of the second control gateway by using the inductor; and a third end of the first control gateway is connected to the first power transistor, and a third end of the second control gateway is connected to the second power transistor. The resonant gate driver according to an embodiment of the present invention can reduce a driving period and increase a response speed.

Abstract: A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 . . . , I2k?1, and I2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1, . . . , Ok?2, and Ok?1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O0=I0 if I0=I1, and O0=I2 otherwise; and when k>1, set Ok?1=I2k?1 if Ok?2=I2k?1, and Ok?1=I2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.