Abstract: An array substrate, a manufacturing method thereof, and a display panel thereof are disclosed. The array substrate includes: an underlay; a first insulation layer; a first active layer; a protective layer; a first gate electrode disposed on the first active layer at an interval from the protective layer; a second insulation layer; and a first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode are connected to the protective layer through first via holes in the second insulation layer; wherein a material of the protective layer includes indium tin oxide or indium gallium zinc oxide.

Abstract: The present application discloses a display panel and a display device. A first metal layer includes at least one first signal transmitting portion. An insulating layer includes a protrusion portion covering the first signal transmitting portion. A second metal layer includes at least one second signal transmitting portion. The second signal transmitting portion includes a first sub-portion, a second sub-portion, and a third sub-portion. The second sub-portion and the third sub-portion are respectively connected to two ends of the first sub-portion. A conductive layer includes a bridging portion. An orthographic projection of the second sub-portion on a substrate and an orthographic projection of the third sub-portion on the substrate both fall outside a coverage of an orthographic projection of the protrusion portion on the substrate. Two ends of the bridging portion are electrically connected to the second sub-portion and the third sub-portion respectively.

Abstract: A display panel and a display device are provided, wherein an insulating layer covers a substrate and a first metal layer, and wherein the insulating layer includes a protruding portion covering a first signal transmission portion. A second metal layer is disposed on a side of the insulating layer away from the first metal layer and includes a second signal transmission portion, wherein the second signal transmission portion covers at least part of a sidewall of the protruding portion. The protruding portion includes a first sub-layer, a second sub-layer, and a first hole arranged at a sidewall of the protruding portion, wherein the first sub-layer is positioned on a side of the second sub-layer away from the first signal transmission portion, and wherein the second signal transmission portion extends into the first hole and contacts the second sub-layer.

Abstract: The present disclosure discloses a pixel circuit and a liquid crystal display panel. The pixel circuit includes a main TFT and a sub-TFT connected in parallel. A resistance of the main TFT is less than a resistance of the sub-TFT. a voltage applied to the sub-TFT is less than a voltage applied to the main TFT by utilizing a voltage dividing function operated by the main TFT and the sub-TFT. The liquid crystal display panel includes the above-mentioned pixel circuit. The present disclosure can achieve different brightness of different domains by utilizing only two TFTs. Therefore, color shifting and transmittance of the panel is improved.

Abstract: A display panel is provided. A first metal layer is patterned to form a first electrode and a second metal layer is patterned to form a second electrode. A projection of the second electrode and a projection of the first electrode are overlapped on a substrate. A gate insulating layer is disposed between the first metal layer and the second metal layer. A test circuit layer is electrically connected to the second electrode. An electrostatic test electrode includes a first test electrode and a second test electrode. The first test electrode is electrically connected to the first electrode and the second test electrode is electrically connected to the test circuit layer. The gate insulating layer disposed in an intermediate region has an antistatic ability.

Abstract: A liquid crystal display panel and a preparation method thereof, the liquid crystal display panel includes: a first substrate including an active display area and an inactive display area; a second substrate disposed opposite to the first substrate; a thin film transistor layer including a gate electrode layer, a gate insulating layer, an active layer, and a source and drain layer; a first passivation layer; a color photoresist layer; a planarization layer; a pixel electrode layer; a liquid crystal layer; and a second passivation layer disposed between the planarization layer and the liquid crystal layer of the active display area.

Abstract: The disclosure discloses a manufacturing method of a liquid crystal display grating. The method includes preparing a substrate, depositing a transparent film layer on the substrate, patterning the transparent film layer for producing a plurality of containing grooves, depositing a liquid crystal alignment film in the containing grooves, injecting liquid crystal molecules in the containing grooves, aligning and packaging the liquid crystal molecules. The disclosure can achieve 3D display by the method above.

Abstract: The present disclosure provides a stage-number reduced gate driver on array (GOA) circuit and a display device. The circuit includes one or more stages of GOA sub-circuits. Each stage of GOA sub-circuits includes a gate signal input end, an original output end, one or more sub-output ends, and one or more branching devices respectively corresponding to the one or more sub-output ends. The gate signal input end and the original output end are respectively connected to a branching node. One end of the one or more branching devices is respectively connected to the branching node. Another end of the one or more branching devices is connected to the corresponding one or more sub-output ends. The present disclosure can solve the problem of excessive length of the GOA circuit in high-resolution model which is not conducive to a narrow bezel design.

Abstract: The present disclosure provides a stage-number reduced gate driver on array (GOA) circuit and a display device. The circuit includes one or more stages of GOA sub-circuits. Each stage of GOA sub-circuits includes a gate signal input end, an original output end, one or more sub-output ends, and one or more branching devices respectively corresponding to the one or more sub-output ends. The gate signal input end and the original output end are respectively connected to a branching node. One end of the one or more branching devices is respectively connected to the branching node. Another end of the one or more branching devices is connected to the corresponding one or more sub-output ends. The present disclosure can solve the problem of excessive length of the GOA circuit in high-resolution model which is not conducive to a narrow bezel design.

Abstract: The disclosure discloses a manufacturing method of a liquid crystal display grating. The method includes preparing a substrate, depositing a transparent film layer on the substrate, patterning the transparent film layer for producing a plurality of containing grooves, depositing a liquid crystal alignment film in the containing grooves, injecting liquid crystal molecules in the containing grooves, aligning and packaging the liquid crystal molecules. The disclosure can achieve 3D display by the method above.

Abstract: The present invention provides a flexible OLED and a manufacture method thereof. The flexible OLED is capable of decreasing the resistance of the second electrode (12) and increasing the conducting ability to even the voltages of respective pixels, to improve the display homogeneity, and meanwhile, capable of reducing the thickness of the second electrode (12) and saving the material of the second electrode (12) by covering the auxiliary conducting layer (13) on the second electrode (12). The manufacture method of the flexible OLED is capable of decreasing the resistance of the second electrode (12) and increasing the conducting ability to even the voltages of respective pixels, to improve the display homogeneity, and meanwhile, capable of reducing the thickness of the second electrode (12) and saving the material of the second electrode (12) by forming the auxiliary conducting layer (13) on the second electrode (12) to cover the second electrode (12).

Abstract: The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42).

Abstract: The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42).

Abstract: The present invention provides a flexible OLED and a manufacture method thereof. The flexible OLED is capable of decreasing the resistance of the second electrode (12) and increasing the conducting ability to even the voltages of respective pixels, to improve the display homogeneity, and meanwhile, capable of reducing the thickness of the second electrode (12) and saving the material of the second electrode (12) by covering the auxiliary conducting layer (13) on the second electrode (12). The manufacture method of the flexible OLED is capable of decreasing the resistance of the second electrode (12) and increasing the conducting ability to even the voltages of respective pixels, to improve the display homogeneity, and meanwhile, capable of reducing the thickness of the second electrode (12) and saving the material of the second electrode (12) by forming the auxiliary conducting layer (13) on the second electrode (12) to cover the second electrode (12).