Patents by Inventor Yaniv Iarovici
Yaniv Iarovici has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9389673Abstract: A method includes entering a hibernation mode in a data storage device with a controller, a non-volatile memory, and a volatile memory having a first portion and a second portion. The hibernation mode is entered by copying, to the second portion, data that is in the first portion and that is flagged to remain available at the volatile memory during the hibernation mode, and powering off the first portion while maintaining power to the second portion.Type: GrantFiled: December 22, 2011Date of Patent: July 12, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Daniel Zvi Yerushalmi, Yaniv Iarovici
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Patent number: 9092150Abstract: A method includes determining, based on an indication from a host device operatively coupled to a data storage device that includes a controller, a non-volatile memory including a hibernate area, a volatile memory, a non-volatile memory interface, and a volatile memory interface, that the data storage device is to enter a low-power state. The method includes, in response to determining that the data storage device is to enter a low-power state, performing a data save operation. The data save operation bypasses the non-volatile memory interface and the volatile memory interface and copies data from the volatile memory of the data storage device to the hibernate area of the non-volatile memory of the data storage device.Type: GrantFiled: December 22, 2011Date of Patent: July 28, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Daniel Zvi Yerushalmi, Yaniv Iarovici
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Patent number: 9069551Abstract: A method may be performed by an electronic device coupled to a volatile system memory. The method includes entering a hibernation mode of the electronic device, where in the hibernation mode, the volatile system memory is powered off. The method further includes detecting a triggering event and, in response to detecting the triggering event, exiting the hibernation mode. While exiting the hibernation mode, the volatile system memory is powered and a pre-hibernation state of the volatile system memory is restored.Type: GrantFiled: December 22, 2011Date of Patent: June 30, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Yaniv Iarovici, Daniel Zvi Yerushalmi, Itzhak Pomerantz, Rahav Yairi
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Patent number: 8914594Abstract: A method may be performed in a data storage device that includes a controller, a non-volatile memory, and a volatile memory. The method includes loading a first portion of stored data from the non-volatile memory to the volatile memory according to one or more load priority indicators accessible to the controller. The method further includes, in response to completion of the loading of the first portion of the stored data to the volatile memory and prior to completion of loading a second portion of the stored data to the volatile memory, sending a signal to indicate to a host device operatively coupled to the data storage device that the volatile memory is ready for use by the host device.Type: GrantFiled: December 22, 2011Date of Patent: December 16, 2014Assignee: SanDisk Technologies Inc.Inventors: Daniel Zvi Yerushalmi, Yaniv Iarovici
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Publication number: 20130166819Abstract: A method may be performed in a data storage device that includes a controller, a non-volatile memory, and a volatile memory. The method includes loading a first portion of stored data from the non-volatile memory to the volatile memory according to one or more load priority indicators accessible to the controller. The method further includes, in response to completion of the loading of the first portion of the stored data to the volatile memory and prior to completion of loading a second portion of the stored data to the volatile memory, sending a signal to indicate to a host device operatively coupled to the data storage device that the volatile memory is ready for use by the host device.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: DANIEL ZVI YERUSHALMI, YANIV IAROVICI
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Publication number: 20130166932Abstract: A method may be performed by an electronic device coupled to a volatile system memory. The method includes entering a hibernation mode of the electronic device, where in the hibernation mode, the volatile system memory is powered off. The method further includes detecting a triggering event and, in response to detecting the triggering event, exiting the hibernation mode. While exiting the hibernation mode, the volatile system memory is powered and a pre-hibernation state of the volatile system memory is restored.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yaniv IAROVICI, Daniel Zvi YERUSHALMI, Itzhak POMERANTZ, Rahav YAIRI
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Publication number: 20130166866Abstract: A method includes entering a hibernation mode in a data storage device with a controller, a non-volatile memory, and a volatile memory having a first portion and a second portion. The hibernation mode is entered by copying, to the second portion, data that is in the first portion and that is flagged to remain available at the volatile memory during the hibernation mode, and powering off the first portion while maintaining power to the second portion.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: DANIEL ZVI YERUSHALMI, YANIV IAROVICI
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Publication number: 20130166864Abstract: A method includes determining, based on an indication from a host device operatively coupled to a data storage device that includes a controller, a non-volatile memory including a hibernate area, a volatile memory, a non-volatile memory interface, and a volatile memory interface, that the data storage device is to enter a low-power state. The method includes, in response to determining that the data storage device is to enter a low-power state, performing a data save operation. The data save operation bypasses the non-volatile memory interface and the volatile memory interface and copies data from the volatile memory of the data storage device to the hibernate area of the non-volatile memory of the data storage device.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: DANIEL ZVI YERUSHALMI, YANIV IAROVICI
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Patent number: 8301824Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.Type: GrantFiled: July 22, 2010Date of Patent: October 30, 2012Assignee: SanDisk IL Ltd.Inventors: Yacov Duzly, Nir Perry, Yaniv Iarovici, Eitan Mardiks
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Patent number: 8296495Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.Type: GrantFiled: August 31, 2010Date of Patent: October 23, 2012Assignee: SanDisk IL Ltd.Inventors: Yacov Duzly, Nir Perry, Yaniv Iarovici, Eitan Mardiks
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Publication number: 20120023298Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.Type: ApplicationFiled: August 31, 2010Publication date: January 26, 2012Inventors: Yacov Duzly, Nir Perry, Yaniv Iarovici, Eitan Mardiks
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Publication number: 20120023297Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.Type: ApplicationFiled: July 22, 2010Publication date: January 26, 2012Inventors: Yacov Duzly, Nir Perry, Yaniv Iarovici, Eitan Mardiks