Patents by Inventor Yaniv Strassberg
Yaniv Strassberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230351021Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.Type: ApplicationFiled: July 9, 2023Publication date: November 2, 2023Inventors: Mor Hoyda Sfadia, Yuval Itkin, Ahmad Atamli, Ariel Shahar, Yaniv Strassberg, Itsik Levi
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Patent number: 11741232Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.Type: GrantFiled: February 1, 2021Date of Patent: August 29, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Mor Hoyda Sfadia, Yuval Itkin, Ahmad Atamli, Ariel Shahar, Yaniv Strassberg, Itsik Levi
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Patent number: 11734005Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.Type: GrantFiled: July 4, 2021Date of Patent: August 22, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Zachy Haramaty, Yaniv Strassberg, Itsik Levi, Alon Singer
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Patent number: 11681635Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.Type: GrantFiled: September 7, 2020Date of Patent: June 20, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yuval Itkin, Yaniv Strassberg, Guy Harel, Ahmad Atamlh
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Publication number: 20230004392Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.Type: ApplicationFiled: July 4, 2021Publication date: January 5, 2023Inventors: Zachy Haramaty, Yaniv Strassberg, Itsik Levi, Alon Singer
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Publication number: 20220245251Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.Type: ApplicationFiled: February 1, 2021Publication date: August 4, 2022Inventors: Mor Hoyda Sfadia, Yuval Itkin, Ahmad Atamli, Ariel Shahar, Yaniv Strassberg, Itsik Levi
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Patent number: 11336273Abstract: An Integrated Circuit (IC) includes functional circuitry and attack-protection circuitry (APC). The functional circuitry is to receive a supply voltage from a power-supply input. The APC is coupled to the power-supply input and includes a front-end circuit and an averaging circuit. The front-end circuit is to compare the supply voltage to a plurality of voltage thresholds, and to output a respective plurality of indications that indicate whether the supply voltage violates the respective voltage thresholds. The averaging circuit is to estimate, for a selected subset of the indications, respective duty-cycles at which the indications in the subset exceed the respective voltage thresholds. The APC is to trigger one or more attack detection events in response to the indications and the duty-cycles.Type: GrantFiled: September 2, 2021Date of Patent: May 17, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan Finkelshtein, Aviv Hasson, Yaniv Strassberg, Ran Sela
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Publication number: 20220075737Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.Type: ApplicationFiled: September 7, 2020Publication date: March 10, 2022Inventors: Yuval Itkin, Yaniv Strassberg, Guy Harel, Ahmad Atamlh
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Patent number: 10496582Abstract: An Integrated Circuit (IC) includes two or more subsystem circuits, a multiplexed bus, a multiplexer/de-multiplexer (MUX/DEMUX) and a logic circuit. The subsystems are independent of one another and are configured to communicate data over multiple General-Purpose Input-Output (GPIO) ports. The multiplexed bus is configured to communicate with circuitry external to the IC. The MUX/DEMUX is configured to translate between the data communicated by the subsystem circuits over the multiple GPIO ports and the multiplexed bus. The logic circuit is independent of the subsystem circuits and is configured to allocate resources of the MUX/DEMUX among the subsystem circuits in response to requests received from the subsystem circuits, and to configure the MUX/DEMUX to provide the allocated resources to the subsystem circuits.Type: GrantFiled: September 6, 2018Date of Patent: December 3, 2019Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yuval Itkin, Yaniv Strassberg