Abstract: The present invention provides a method for treating a copper-containing waste etching solution, which includes: preparing basic copper chloride nanometer seed crystals and synthesizing basic copper chloride mono-crystals; making an acidic waste etching solution subjected to agglomeration reaction with an ammonium-containing solution and slurry containing the basic copper chloride mono-crystals to obtain basic copper chloride crystal particles and copper-removed waste solution; making an alkaline waste etching solution react with sulfuric acid to obtain a copper sulfate mixed solution; and then evaporating, concentrating, cooling and crystallizing the copper sulfate mixed solution obtained by the reaction of the alkaline waste etching solution and the sulfuric acid in sequence to obtain copper sulfate pentahydrate solids.

Abstract: A level shifter includes a latch circuit having a first FET and a second FET; an input circuit having a third FET and a fourth FET, the gates of the first and second FETs being coupled to the drains of the fourth and third FETs, respectively; a first resistive device (resistor, diode-connected FET) coupled between and in series with the first and third FETs between a first voltage rail and a second voltage rail; and a second resistive device (resistor, diode-connected FET) coupled between and in series with the second and fourth FETs between the first and second voltage rails. The gates of the third and fourth FETs are configured to receive a first set of complementary voltages, and a second set of complementary voltages are configured to be generated at the gates of the first and second FETs, respectively. The second set of complementary voltages are based on the first set of complementary voltages.

Abstract: A level shifter includes a latch circuit having a first FET and a second FET; an input circuit having a third FET and a fourth FET, the gates of the first and second FETs being coupled to the drains of the fourth and third FETs, respectively; a first resistive device (resistor, diode-connected FET) coupled between and in series with the first and third FETs between a first voltage rail and a second voltage rail; and a second resistive device (resistor, diode-connected FET) coupled between and in series with the second and fourth FETs between the first and second voltage rails. The gates of the third and fourth FETs are configured to receive a first set of complementary voltages, and a second set of complementary voltages are configured to be generated at the gates of the first and second FETs, respectively. The second set of complementary voltages are based on the first set of complementary voltages.