Abstract: The present disclosure is directed to improving compatibility between chiplets integrated with disparate chiplet interfaces. To reduce compatibility issues due non-matching bump maps, a dual-mode bump map assignment may be implemented to enable a chiplet to utilize multiple signal number sequence assignments. Additionally, a modularized Advanced Interface Bus (AIB) interface may be implemented to reduce channel mismatch in AIB -UCIe multi-channel interoperability.

Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.

Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.

Abstract: One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.

Abstract: One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.

Abstract: Systems and methods for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. A power distribution network may supply power to components of an integrated circuit, and data driver circuitry may draw first current to drive a serial data signal generated from a parallel data signal. Compensation circuitry may receive the parallel data signal and draw second current at times when the compensation circuitry determines data driver circuitry is not drawing the first current based on the parallel data signal, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device.

Abstract: A driver circuit includes unit slice circuits that generate an output data signal based on an input data signal. The driver circuit reduces a voltage swing of the output data signal without changing a termination resistance of the driver circuit in response to decreasing a number of the unit slice circuits that generate the output data signal based on the input data signal.

Abstract: Techniques and mechanisms determine latencies of transmitters of transceivers and use the determined latencies to adjust latencies of the transmitters. For example, a test pattern may be used to determine a first transmitter has a higher latency than a second transmitter. The second transmitter may be provided data indicating a delay to increase its latency such that it matches the first transmitter.

Abstract: Systems and methods of calibrating a successive approximation register analog-to-digital converter (ADC) are disclosed. A plurality of capacitor stages, a first capacitor array, and a first capacitor stage are coupled in parallel. A capacitance of the first capacitor stage is compared to a sum of capacitances of the plurality of capacitor stages and of the first capacitor array. In response to the comparing, the capacitance of the first capacitor stage is increased by increasing the capacitance of a second capacitor array if the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

Abstract: One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

Abstract: Systems and methods of calibrating a successive approximation register analog-to-digital converter (ADC) are disclosed. A plurality of capacitor stages, a first capacitor array, and a first capacitor stage are coupled in parallel. A capacitance of the first capacitor stage is compared to a sum of capacitances of the plurality of capacitor stages and of the first capacitor array. In response to the comparing, the capacitance of the first capacitor stage is increased by increasing the capacitance of a second capacitor array if the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract: A buffer circuit includes first and second inputs and first and second outputs. The buffer circuit is configurable to buffer a differential input signal received at the first and the second inputs to generate a differential output signal at the first and the second outputs in a current mode logic buffer mode based on a control signal. The buffer circuit is configurable to buffer the differential input signal to generate the differential output signal in an H-bridge buffer mode based on the control signal.

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract: A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circuit coupled to the first and the second resistors. The third switch circuit couples the first and the second resistors to a node at a first voltage when the buffer circuit is configured to function in a current mode logic buffer mode. The third switch circuit couples the first and the second resistors to a node at a second voltage when the buffer circuit is configured to function in an H-bridge buffer mode.

Abstract: The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.

Abstract: The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of a charge pump and provides a signal to a digital control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). The analog comparator with the digital control circuit changes the VCO loads to select the best VCO range to achieve the incoming signal frequency lock. A single PLL with the VCO load selection method disclosed, with use of built-in hysteresis, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges to be covered in a stable fashion. This enables frequency locking of the PLL over a wide range of frequencies with a small die size and low power consumption.

Abstract: The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.

Abstract: The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of the charge pump voltage and provides an signal to a control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). This analog comparator with the digital control circuit is used to cause a change in the VCO loads, from a multiplicity of loads, and select the best VCO range to achieve the incoming signal frequency lock. The use of a single PLL with the analog comparator output to control the VCO load selection, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges of the multiple tunable loads of the VCO to be covered with one PLL. This reduces the die size and power consumption compared to a circuit implementation using the standard PLL for the wider frequency range of operation.

Abstract: High Definition Multimedia Interface (HDMI) receivers use digital multiplexer at the input stage after equalization, clock and data recovery for each channel of each port. Described herein is the use of an analog multiplexer for HDMI receiver. The purpose of the analog multiplexer is to reduce the die size and power consumption by selecting the input signal from one port out of a set of input ports, right after the equalization and hence use only one block of clock and data recovery (CDR) circuits for the receiver. This sharing of one block of CDR circuits between all input ports requires the use of analog multiplexer circuits, as the signals presented to the analog multiplexer after equalization are of low signal strength and have insufficient signal-to-noise ratio to allow handling by digital multiplexer circuitry.