Patents by Inventor YANLEI PING

YANLEI PING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and manufacturing method thereof
    Patent number: 11011703
    Abstract: This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; a bitline, suspended on the substrate; a bottom electrode, wrapped around the bitline; a resistive layer, wrapped around the bottom electrode; a top electrode, wrapped around the resistive layer; and a wordline electrode, disposed around the top electrode and connected to the top electrode.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 18, 2021
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Qiang Ma, Yanlei Ping, Tianhui Li
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200259082
    Abstract: This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; a bitline, suspended on the substrate; a bottom electrode, wrapped around the bitline; a resistive layer, wrapped around the bottom electrode; a top electrode, wrapped around the resistive layer; and a wordline electrode, disposed around the top electrode and connected to the top electrode.
    Type: Application
    Filed: November 13, 2019
    Publication date: August 13, 2020
    Inventors: QIANG MA, YANLEI PING, TIANHUI LI
  • Metal silicide layer, NMOS transistor, and fabrication method
    Patent number: 8865593
    Abstract: Exemplary embodiments provide materials and methods for forming a metal silicide layer and/or an NMOS transistor. The metal silicide layer can be formed by heating a metal layer containing at least a tellurium element on a semiconductor substrate. The metal silicide layer can thus contain at least the tellurium element on the semiconductor substrate. The metal silicide layer can be formed in an NMOS transistor. With the addition of tellurium element in the metal silicide layer, Schottky barrier height between the metal silicide layer and the underling semiconductor substrate can be reduced. Contact resistance of the NMOS transistor can also be reduced.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Manufacturing International Corp
    Inventors: Haibo Xiao, Wayne Bao, Yanlei Ping
  • METAL SILICIDE LAYER, NMOS TRANSISTOR, AND FABRICATION METHOD
    Publication number: 20130341687
    Abstract: Exemplary embodiments provide materials and methods for forming a metal silicide layer and/or an NMOS transistor. The metal silicide layer can be formed by heating a metal layer containing at least a tellurium element on a semiconductor substrate. The metal silicide layer can thus contain at least the tellurium element on the semiconductor substrate. The metal silicide layer can be formed in an NMOS transistor. With the addition of tellurium element in the metal silicide layer, Schottky barrier height between the metal silicide layer and the underling semiconductor substrate can be reduced. Contact resistance of the NMOS transistor can also be reduced.
    Type: Application
    Filed: October 18, 2012
    Publication date: December 26, 2013
    Inventors: HAIBO XIAO, WAYNE BAO, YANLEI PING