Patents by Inventor Yanmei Tian

Yanmei Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100033211
    Abstract: With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.
    Type: Application
    Filed: October 13, 2009
    Publication date: February 11, 2010
    Inventors: Harry Muljono, Stefan Rusu, Yanmei Tian, Mubeen Atha, David J. Ayers
  • Patent number: 7609091
    Abstract: With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: October 27, 2009
    Assignee: Intel Corporation
    Inventors: Harry Muljono, Stefan Rusu, Yanmei Tian, Mubeen Atha, David J. Ayers
  • Publication number: 20090248945
    Abstract: In some embodiments, a circuit is provided with a transmitter to generate switching noise during clock events when no transition occurs to reduce data dependent switching noise.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Navindra Navaratnam, Edward Burton, Mahadev Nemani, Yanmei Tian, Harry Muljono
  • Publication number: 20070139070
    Abstract: For one disclosed embodiment, a driver may generate an output signal on a line. A predriver may receive an input signal and control the driver in response to the input signal to help improve symmetry of rise and fall transitions in the output signal. Other embodiments are also disclosed.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 21, 2007
    Inventors: Yanmei Tian, Marlene Chan, Mohammed Atha, Harry Muljono
  • Patent number: 7218148
    Abstract: In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a unity gain detector to traverse a gain curve of an output buffer circuit to determine unity gain voltages associated with unity gain crossover points on an input voltage ramp. The apparatus further includes a pre-boost circuit to apply the unity gain voltages to at least one input/output buffer within the output buffer circuit.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: May 15, 2007
    Assignee: Intel Corporation
    Inventors: Yanmei Tian, Yanbin Wang, Mubeen Atha, Harry Muljono
  • Publication number: 20070071111
    Abstract: With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Inventors: Harry Muljono, Stefan Rusu, Yanmei Tian, Mubeen Atha, David Ayers
  • Patent number: 7180345
    Abstract: A method and an apparatus to provide time-based edge-rate compensation have been disclosed. In one embodiment, the apparatus includes a reference pad, a reference circuit coupled to the reference pad, the reference circuit being operable to charge and to discharge a reference voltage at the reference pad, and an edge-rate detection and measurement circuit coupled to the reference pad to detect and to measure an edge-rate of the reference voltage at the reference pad. Other embodiments have been claimed and described.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Mohammed M. Atha, Yanmei Tian, Harry Muljono
  • Publication number: 20070001725
    Abstract: A method and an apparatus to provide time-based edge-rate compensation have been disclosed. In one embodiment, the apparatus includes a reference pad, a reference circuit coupled to the reference pad, the reference circuit being operable to charge and to discharge a reference voltage at the reference pad, and an edge-rate detection and measurement circuit coupled to the reference pad to detect and to measure an edge-rate of the reference voltage at the reference pad. Other embodiments have been claimed and described.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Mohammed Atha, Yanmei Tian, Harry Muljono
  • Patent number: 7057672
    Abstract: A high frequency data transmission circuit including design for testability (DFT) features. An integrated circuit includes core control logic to provide a data signal and output drive logic including a local data latch and a transmitter. The data latch receives the data signal and provides true and complementary forms of the data signal to the transmitter over symmetrical signal paths. The transmitter provides an output signal to an external receiver.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Bal S. Sandhu, Yanmei Tian, Chih-Chang Lin
  • Publication number: 20060114026
    Abstract: In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a unity gain detector to traverse a gain curve of an output buffer circuit to determine unity gain voltages associated with unity gain crossover points on an input voltage ramp. The apparatus further includes a pre-boost circuit to apply the unity gain voltages to at least one input/output buffer within the output buffer circuit.
    Type: Application
    Filed: November 30, 2004
    Publication date: June 1, 2006
    Inventors: Yanmei Tian, Yanbin Wang, Mubeen Atha, Harry Muljono
  • Publication number: 20040128601
    Abstract: Arrangements (circuits, methods, systems) having self-measurement of input/output (I/O) specifications (e.g., input trip-point, output drive-level and pin leakage).
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Harry Muljono, Yanmei Tian
  • Publication number: 20020140692
    Abstract: A high frequency data transmission circuit including design for testability (DFT) features. An integrated circuit includes core control logic to provide a data signal and output drive logic including a local data latch and a transmitter. The data latch receives the data signal and provides true and complementary forms of the data signal to the transmitter over symmetrical signal paths. The transmitter provides an output signal to an external receiver.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 3, 2002
    Inventors: Bal S. Sandhu, Yanmei Tian, Chih-Chang Lin