Abstract: A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Abstract: Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

Abstract: Methods of patterning vias and trenches using a polymerization protective liner after forming a lower patterned mask layer used for etching trenches on a semiconductor substrate prior to forming an upper patterned mask layer used for etching vias are provided. Methods involve forming a polymerization protective liner either nonconformally or conformally using silicon tetrachloride and methane polymerization. Polymerization protective liners may be sacrificial.

Abstract: A semiconductor device is provided. The semiconductor device includes a base layer, a first MRAM device formed on the base layer, and a second MRAM device formed on the base layer. The first MRAM device has a different performance characteristic than the second MRAM device.

Abstract: Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

Abstract: A structure comprising: metal lines and viabars that surround a periphery of an active area of a semiconductor device; at least one viabar that extends through multiple layers of the semiconductor device, wherein the at least one viabar connects a metal line of one layer of the structure with a metal line of another layer of the structure; and a connection viabar that terminates at a metal line of a layer between the one layer of the structure and the another layer of the structure, wherein a thickness of the connection viabar is less than a thickness of the at least one viabar.

Abstract: Embodiments of the invention are directed to a computer system having a processor communicatively coupled to a memory. The processor performs processor operations that include accessing an electronic file that includes an electronic integrated circuit (IC) design. The electronic file is operable to control a fabrication system to fabricate an IC according to the electronic IC design. The processor operations further includes applying a bulging predication analysis to the electronic IC design; and making one or more changes to the electronic IC design based at least in part on a result of the bulging prediction analysis.

Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

Abstract: A redistribution layer for an integrated circuit package is provided. The redistribution layer includes a first conductive layer and a second layer disposed directly on the first conductive layer. The first conductive layer has a resistivity of less than 3.6*10?8 ?·m and has a thickness of greater than or equal to 1 ?m. The second layer includes tungsten. An integrated circuit package is also provided that includes the redistribution layer electrically connecting a first integrated circuit of the first integrated circuit package to a first input/output of a frame of the integrated circuit package. The frame is connected to the first integrated circuit. A method for manufacturing a redistribution layer is also provided.

Abstract: A top cap layer covering a first metal line and a second metal line, horizontally between the first metal line and the second metal line is, in sequential order, a post cap liner, an air gap and the post cap liner. A first set of metal lines embedded in an upper surface of a dielectric, a second set of metal lines embedded below the dielectric and above the electronic components, a post cap liner covering the first set of metal lines, a cavity which dissects a first metal line of the first set of metal lines and extends to a second metal line of the second set of metal lines and dissects the second set of metal lines. Forming a cavity in a first metal line embedded in an upper surface of a dielectric, where the first metal line and the dielectric are covered by a top cap layer.

Abstract: A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

Abstract: A MOSFET includes a semiconductor substrate that has a frontside and a backside; a metal gate at the frontside of the substrate; a first source/drain structure at the frontside of the substrate, adjacent to the metal gate in a first direction; and a first source/drain contact at the frontside of the first source/drain structure. Also included are a backside power rail at the backside of the substrate; and a recessed via that connects the first source/drain contact through the substrate to the backside power rail. The recessed via is adjacent to the first source/drain structure in a direction perpendicular to the first direction. A dielectric cap covers a frontside of the first source/drain contact. A gate contact is disposed at a frontside of the dielectric cap. The gate contact at least partly overlies the first source/drain contact.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a lower level via that is fully aligned to an upper level metal line. The lower level via is elongated along a lower level metal line direction and partially recessed.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.

Abstract: A semiconductor structure is presented including a metal layer having a first pattern, a metal bridge located within the first pattern, at least one via disposed on a portion of the metal layer such that the metal bridge extends to a top surface of the at least one via, and a metal cap disposed directly on top of the at least one via disposed on the portion of the metal layer.

Abstract: A method of forming a multi color resist structure includes providing a substrate including an underlayer material; forming a first organic planarizing layer on the substrate; forming a first anti reflecting layer on the first organic planarizing layer, forming and developing a first patterned resist on the first anti reflecting layer; forming a second organic planarizing layer on the first anti reflecting layer and on the first patterned resist; forming a second anti reflecting layer on the second organic planarizing layer and forming and developing the second patterned resist, wherein the first patterned resist is a non-chemically amplified resist (n-CAR) or metal resist and the second patterned resist is CAR organic resist.

Abstract: A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

Abstract: A memory structure including a magnetic tunnel junction (MTJ) structure and a top electrode that are both formed without utilizing ion beam etching is provided. The MTJ structure, which includes a lower magnetic stack, a tunnel barrier layer and an upper magnetic stack, is pyramidal shaped, and end portions of the lower magnetic stack of the MTJ structure are devoid of the tunnel barrier layer and the upper magnetic stack.

Abstract: A semiconductor structure includes a substrate; a spacer protruding from the substrate and surrounding a cavity; and spin-on glass filling a portion of the cavity.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring and a second level of interconnect wiring having a bilayer metal arrangement incorporating via elements, the second level of interconnect wiring electrically connected to the first level of interconnect wiring. In one example, the bilayer metal arrangement of the second level of interconnect wiring includes a first row of bilayer metals and a second row of bilayer metals disposed over the first row of bilayer metals. In another example, the bilayer metal arrangement of the second level of interconnect wiring includes a cap dielectric material for isolation from the first row of the bilayer metal. In yet another embodiment, the bilayer metal arrangement of the second level of interconnect wiring includes a metal bridge.