Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

Abstract: Aspects of the disclosure include method of making semiconductor structures. Aspects include providing a semiconductor structure including a plurality of spacer, an organic planarization layer, and a SiARC layer. Aspects also include forming an inverted mask on the semiconductor structure, the inverted mask including an inverted mask opening above a portion of the plurality of spacers and a portion of the TiN layer. Aspects also include eroding the portion of the plurality of spacers below the inverted mask opening. Aspects also include depositing a fill material masking the portion of the plurality of spacers below the inverted mask opening and the portion of the TiN layer below the inverted mask opening to generate a masked TiN layer segment and an unmasked TiN layer segment and removing a portion of the unmasked TiN layer segment.

Abstract: According to yet another non-limiting embodiment, a fin-type field effect transistor (finFET) including a strained channel region includes a semiconductor substrate extending along a first axis to define a length, a second axis perpendicular to the first axis to width, and a third direction perpendicular to the first and second axes to define a height. At least one semiconductor fin on an upper surface of the semiconductor substrate includes a semiconductor substrate portion on an upper surface of the semiconductor substrate, a strain-inducing portion on an upper surface of the semiconductor substrate portion, and an active semiconductor portion defining a strained channel region on an upper surface of the strain-inducing portion. A first height of the semiconductor substrate portion is greater than a second height of the strain-inducing portion.

Abstract: According to yet another non-limiting embodiment, a fin-type field effect transistor (finFET) including a strained channel region includes a semiconductor substrate extending along a first axis to define a length, a second axis perpendicular to the first axis to width, and a third direction perpendicular to the first and second axes to define a height. At least one semiconductor fin on an upper surface of the semiconductor substrate includes a semiconductor substrate portion on an upper surface of the semiconductor substrate, a strain-inducing portion on an upper surface of the semiconductor substrate portion, and an active semiconductor portion defining a strained channel region on an upper surface of the strain-inducing portion. A first height of the semiconductor substrate portion is greater than a second height of the strain-inducing portion.

Abstract: Aspects of the disclosure include method of making semiconductor structures. Aspects include providing a semiconductor structure including a plurality of spacer, an organic planarization layer, and a SiARC layer. Aspects also include forming an inverted mask on the semiconductor structure, the inverted mask including an inverted mask opening above a portion of the plurality of spacers and a portion of the TiN layer. Aspects also include eroding the portion of the plurality of spacers below the inverted mask opening. Aspects also include depositing a fill material masking the portion of the plurality of spacers below the inverted mask opening and the portion of the TiN layer below the inverted mask opening to generate a masked TiN layer segment and an unmasked TiN layer segment and removing a portion of the unmasked TiN layer segment.

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract: A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded transition layer, a dielectric layer, an inverse graded transition layer, and an oxide layer. In another embodiment, the improved hardmask may be comprised of four layers; an oxide adhesion layer, a graded transition layer, a dielectric layer, and an oxide layer. In another embodiment, a method of forming an improved hardmask may comprise a continuous five step plasma enhanced chemical vapor deposition (PECVD) process utilizing a silicon precursor, a porogen, and oxygen. In yet another embodiment, a method of forming an improved hardmask may comprise a continuous four step PECVD process utilizing a silicon precursor, a porogen, and oxygen.

Abstract: A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded transition layer, a dielectric layer, an inverse graded transition layer, and an oxide layer. In another embodiment, the improved hardmask may be comprised of four layers; an oxide adhesion layer, a graded transition layer, a dielectric layer, and an oxide layer. In another embodiment, a method of forming an improved hardmask may comprise a continuous five step plasma enhanced chemical vapor deposition (PECVD) process utilizing a silicon precursor, a porogen, and oxygen. In yet another embodiment, a method of forming an improved hardmask may comprise a continuous four step PECVD process utilizing a silicon precursor, a porogen, and oxygen.