Patents by Inventor Yann Bogumilowicz
Yann Bogumilowicz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11698488Abstract: A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elemType: GrantFiled: December 19, 2018Date of Patent: July 11, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Fabrice Nemouchi, Charles Baudot, Yann Bogumilowicz, Elodie Ghegin, Philippe Rodriguez
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Patent number: 10622210Abstract: The present invention relates to a method for producing an element of a microelectronic device on a support comprising a base layer, an inserted layer and a covering layer. The method includes forming a confinement volume including an etching of the inserted layer selectively to the base layer and to the covering layer, and filling, by a filling material constituting the element, of at least one part of the confinement volume by an epitaxial growth of the material from the side wall. The formation of the confinement volume comprises a formation of a hole through the whole thickness of the covering layer, and the etching is an anisotropic etching done by applying an etching on the inserted layer through the hole.Type: GrantFiled: September 13, 2018Date of Patent: April 14, 2020Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Rami Khazaka, Yann Bogumilowicz, Herve Boutry
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Patent number: 10354870Abstract: First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions.Type: GrantFiled: November 5, 2015Date of Patent: July 16, 2019Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Yann Bogumilowicz, Jean-Michel Hartmann
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Publication number: 20190187375Abstract: A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elemType: ApplicationFiled: December 19, 2018Publication date: June 20, 2019Inventors: Fabrice NEMOUCHI, Charles BAUDOT, Yann BOGUMILOWICZ, Elodie GHEGIN, Philippe RODRIGUEZ
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Publication number: 20190096671Abstract: The present invention relates to a method for producing an element of a microelectronic device on a support comprising a base layer, an inserted layer and a covering layer. The method includes forming a confinement volume including an etching of the inserted layer selectively to the base layer and to the covering layer, and filling, by a filling material constituting the element, of at least one part of the confinement volume by an epitaxial growth of the material from the side wall. The formation of the confinement volume comprises a formation of a hole through the whole thickness of the covering layer, and the etching is an anisotropic etching done by applying an etching on the inserted layer through the hole.Type: ApplicationFiled: September 13, 2018Publication date: March 28, 2019Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Rami KHAZAKA, Yann Bogumilowicz, Herve Boutry
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Publication number: 20180261454Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.Type: ApplicationFiled: June 27, 2016Publication date: September 13, 2018Inventors: Xinyu BAO, Zhiyuan YE, Jean-Baptiste PIN, Errol SANCHEZ, Franck BASSANI, Thierry BARON, Yann BOGUMILOWICZ, Jean-Michel HARTMANN
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Patent number: 9733430Abstract: A method of manufacturing an optical waveguide with a vertical slot including the steps of a) providing a substrate successively including an electric insulator layer and a crystalline semiconductor layer, b) forming a trench on the semiconductor layer to expose the electric insulator layer and defining first and second semiconductor areas on either side, step b) being executed so that the first semiconductor area has a lateral edge extending across the entire thickness of the semiconductor layer, c) forming the dielectric layer having the predetermined width across the entire thickness of the lateral edge, the method being remarkable in that the trench formed at step b) is configured so that the second semiconductor area forms a seed layer.Type: GrantFiled: August 11, 2015Date of Patent: August 15, 2017Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Jean-Marc Fedeli, Alexis Abraham, Ségoléne Olivier, Yann Bogumilowicz, Thomas Magis, Pierre Brianceau
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Publication number: 20170004968Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.Type: ApplicationFiled: June 27, 2016Publication date: January 5, 2017Inventors: Xinyu BAO, Zhiyuan YE, Jean-Baptiste PIN, Errol SANCHEZ, Franck BASSANI, Thierry BARON, Yann BOGUMILOWICZ, Jean-Michel HARTMANN
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Publication number: 20160126095Abstract: First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions.Type: ApplicationFiled: November 5, 2015Publication date: May 5, 2016Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Yann BOGUMILOWICZ, Jean-Michel HARTMANN
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Publication number: 20160041339Abstract: A method of manufacturing an optical waveguide with a vertical slot including the steps of a) providing a substrate successively including an electric insulator layer and a crystalline semiconductor layer, b) forming a trench on the semiconductor layer to expose the electric insulator layer and defining first and second semiconductor areas on either side, step b) being executed so that the first semiconductor area has a lateral edge extending across the entire thickness of the semiconductor layer, c) forming the dielectric layer having the predetermined width across the entire thickness of the lateral edge, the method being remarkable in that the trench formed at step b) is configured so that the second semiconductor area forms a seed layer.Type: ApplicationFiled: August 11, 2015Publication date: February 11, 2016Inventors: Jean-Marc FEDELI, Alexis ABRAHAM, Ségoléne OLIVIER, Yann BOGUMILOWICZ, Thomas MAGIS, Pierre BRIANCEAU
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Patent number: 9246045Abstract: Fabrication of a photodetector is performed on a substrate comprising a first portion successively provided with a first semiconductor film, an electrically insulating layer, a second semiconductor film, and a protection layer. The substrate also comprises a second portion not comprising the second semiconductor film. It further comprises a third portion not comprising the second semiconductor film and the protection layer. The second semiconductor film is etched in the first portion to form a cavity. A PIN/NIP diode is formed in the third portion at least by means of deposition of a third semiconductor material which also comes and fills the cavity. A conversion layer is deposited to absorb a light signal originating from the second semiconductor film and to convert the light signal into an electric signal, the conversion layer electrically connecting the PIN/NIP diode.Type: GrantFiled: December 15, 2014Date of Patent: January 26, 2016Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Jean-Michel Hartmann, Yann Bogumilowicz, Jean-Marc Fedeli
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Publication number: 20150171259Abstract: Fabrication of a photodetector is performed on a substrate comprising a first portion successively provided with a first semiconductor film, an electrically insulating layer, a second semiconductor film, and a protection layer. The substrate also comprises a second portion not comprising the second semiconductor film. It further comprises a third portion not comprising the second semiconductor film and the protection layer. The second semiconductor film is etched in the first portion to form a cavity. A PIN/NIP diode is formed in the third portion at least by means of deposition of a third semiconductor material which also comes and fills the cavity. A conversion layer is deposited to absorb a light signal originating from the second semiconductor film and to convert the light signal into an electric signal, the conversion layer electrically connecting the PIN/NIP diode.Type: ApplicationFiled: December 15, 2014Publication date: June 18, 2015Inventors: Jean-Michel HARTMANN, Yann BOGUMILOWICZ, Jean-Marc FEDELI
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Patent number: 8962496Abstract: The process for smoothing a rough surface of a first substrate made of a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N is implemented by placing a second substrate facing the first substrate so that the rough surface is placed facing a surface of the second substrate. The first and second substrates are separated by a distance d of at least 10 ?m, the facing portions of the two substrates defining a confinement space. The first substrate is then heated so as to partially desorb one of the elements of said alloy and to reach the saturated vapor pressure of this element in the confinement space and to obtain a surface atom mobility that is sufficient to reduce the roughness of the rough surface.Type: GrantFiled: October 26, 2012Date of Patent: February 24, 2015Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Thomas Jouanneau, Yann Bogumilowicz
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Publication number: 20140315394Abstract: The process for smoothing a rough surface of a first substrate made of a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N is implemented by placing a second substrate facing the first substrate so that the rough surface is placed facing a surface of the second substrate. The first and second substrates are separated by a distance d of at least 10 ?m, the facing portions of the two substrates defining a confinement space. The first substrate is then heated so as to partially desorb one of the elements of said alloy and to reach the saturated vapor pressure of this element in the confinement space and to obtain a surface atom mobility that is sufficient to reduce the roughness of the rough surface.Type: ApplicationFiled: October 26, 2012Publication date: October 23, 2014Applicant: COMMISSARIAT Á L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Thomas Jouanneau, Yann Bogumilowicz