Abstract: A bus control device for a central processing unit (CPU) comprising a plurality of isolatable segments, which permits the transfer of data from one segment to another two adjacent segments being connected with one another via switches (S01, S11, S02, S12) controlled by a selection signal (C12, C23), an amplification device (A1, A2, A3) controlled by an actuation signal (CA1, CA2, CA3) being associated with each bus segment for amplifying the voltages that appear on the lines (B01, B11, B02, B12, B03, B13) of this segment, said control device being characterized in that it includes slaving means (12, 13, 16, 22, 23, 26) for actuating the amplifier of any one segment is response to the actuation of the amplifier of a segment adjacent to the this segment and in reponse to the selection signal (C12, C23) for the switches that connect this segment to said adjacent segment.

Abstract: A sense amplifier device, as of CMOS technology includes a first (AN) and second (AP) amplifier responsive to the voltages (VB0, VB1) of two bit lines (B0, B1) to be amplified. When it is activated, the first amplifier (AN) connects the bit line having the lowest potential to ground potential. When the voltage of one of the bit lines is lower than a threshold voltage (VT), the second amplifier is triggered and connects the bit line having the highest potential to supply voltage.