Abstract: A method and system for identifying a NAND-Flash without reading a device ID. The method includes: executing an identification flow for setting a first page of a block as a target block, utilizing a combinations table to query a target block, evaluating a result by comparing a identifying information in the target block with the combinations table, trying all combinations in the combinations table until correctly identifying the NAND-Flash by having a positive match result or returning an error if none of the combinations match.

Abstract: Task management methods. A plurality of GBL (global bandwidth limiter) classes is provided. One of the GBL classes is selected based on the priority of a first task, in which the first task is from a MCU (micro-controller unit) bus. A system GBL class is selected based on the highest GBL class which has been selected among the GBL classes. A bandwidth limiter of a DMA (direct memory access) unit is assigned according to the system GBL class and the priority of a second task if the DMA unit is activated by the second task. The second task is from a DMA bus, and the cycle between the DMA and MCU buses is determined according to the bandwidth limiter.

Abstract: A memory disposition system, comprising a first memory device and a second memory device. First and second memory devices are provided to a system, such as an embedded system. The first and the second memory devices are coupled to a control unit, such as micro control unit. The first memory device stores first programs and the second memory device second programs. The first and second programs are controlled by the control unit. The first memory device can be a one time programmable memory device, such as a ROM, and the second memory device a multiple times programmable memory device, such as a flash memory.

Abstract: A method and system for identifying a NAND-Flash without reading a device ID. The method includes: executing an identification flow for setting a first page of a block as a target block, utilizing a combinations table to query a target block, evaluating a result by comparing a identifying information in the target block with the combinations table, trying all combinations in the combinations table until correctly identifying the NAND-Flash by having a positive match result or returning an error if none of the combinations match.

Abstract: Exception analysis methods for embedded systems. System exceptions from an embedded system with an operating system are received. Each system exception comprises first error code portion and second error code portion. The system exceptions are classified into error categories according to the first error code portion. The categories are based on components of the operating system of the embedded system. Each error category includes error types. The system exceptions are then analyzed to determine the error types of the system exceptions according to the classified error categories and the second error code portion.

Abstract: A memory disposition system, comprising a first memory device and a second memory device. First and second memory devices are provided to a system, such as an embedded system. The first and the second memory devices are coupled to a control unit, such as micro control unit. The first memory device stores first programs and the second memory device second programs. The first and second programs are controlled by the control unit. The first memory device can be a one time programmable memory device, such as a ROM, and the second memory device a multiple times programmable memory device, such as a flash memory.

Abstract: Task management methods. A plurality of GBL (global bandwidth limiter) classes is provided. One of the GBL classes is selected based on the priority of a first task, in which the first task is from a MCU (micro-controller unit) bus. A system GBL class is selected based on the highest GBL class which has been selected among the GBL classes. A bandwidth limiter of a DMA (direct memory access) unit is assigned according to the system GBL class and the priority of a second task if the DMA unit is activated by the second task. The second task is from a DMA bus, and the cycle between the DMA and MCU buses is determined according to the bandwidth limiter.