Patents by Inventor Yann Gazounaud

Yann Gazounaud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8156396
    Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: April 10, 2012
    Inventors: Jean-Yann Gazounaud, Howard Maassen
  • Patent number: 7810005
    Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 5, 2010
    Assignee: Credence Systems Corporation
    Inventors: Jean-Yann Gazounaud, Howard Maassen
  • Patent number: 7035755
    Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: April 25, 2006
    Assignee: Credence Systems Corporation
    Inventors: Michael F. Jones, Robert Whyte, Jamie S. Cullen, Naveed Zaman, Yann Gazounaud, Burnell G. West, William Fritzsche
  • Patent number: 6694432
    Abstract: Securing data stored in an electronic component test machine which includes a central processor unit provided with storage means, and a local memory connected to the storage means via a transmission bus. At least one file of test vectors is created to perform the component test. Data contained in the file of test vectors is encrypted. The encrypted test vector file is stored in the storage means of the central processor unit. Prior to each test, the encrypted test vector file is loaded into the local memory via the transmission bus, and then the encrypted data of the test vector files is decrypted and stored in the local memory from where it is retrieved so that the test can be performed. While unencrypted data is stored in the local memory component, access to it by the operator is blocked so that sensitive information contained therein remains secure.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: February 17, 2004
    Assignee: Schlumberger Systémes
    Inventors: Yann Gazounaud, Max Wach
  • Publication number: 20030105607
    Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.
    Type: Application
    Filed: August 16, 2002
    Publication date: June 5, 2003
    Inventors: Michael F. Jones, Robert Whyte, Jamie S. Cullen, Naveed Zaman, Yann Gazounaud, Burnell G. West