Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.

Abstract: The invention relates to a method of processing data frames arriving on a network interface, comprising the following steps implemented in the network interface: storing a set of target positions (tgtPOS), positions in a frame at which are expected at least one parameter characterizing a subframe (ETH_TYPE) and parameters (SRC_IP, DST_IP) characterizing a client-server session; storing an expected value (xpVAL) for the subframe parameter; receiving a current frame and comparing the value (xtVAL) received at the position of the subframe parameter to the expected value; if equal, calculating an index (IDX) from the values received at the positions of the session parameters; and routing the current frame to a processing resource associated with the index.

Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.

Abstract: A system comprising a peripheral having a timing mechanism and a node, one of which comprises a real memory space and the other a corresponding virtual memory space, is disclosed. On receiving a timing command in the real memory space, comprising references to an event and time, an entry comprising data relative to the event and time references is created in a monitoring queue of the peripheral. A current point in time is then compared, in the peripheral, to a scheduled point in time linked to an item of data relative to a time reference stored in the monitoring queue. In response, if the current point in time is after the scheduled point in time, an item of data relative to a reference linked to the item of data relative to a time reference stored in the monitoring queue is stored in the real memory space.

Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.

Abstract: The invention relates in particular to the optimization of routing in a cluster comprising a plurality of nodes and static communication links connecting nodes of the plurality of nodes, said routing being based on load levels associated with the communication links. In order to establish a connection between at least two nodes of the cluster that have been identified (505), at least one route is determined (510) that connects the identified nodes according to the communication links, said route being determined according to the nodes identified, communication links and at least one load level associated with each communication link. A determined route is selected. Subsequently, a value of weight associated with the selected route is estimated (520) and a load level associated with each communication link of the selected route is incremented (525).

Abstract: The invention relates to a method of processing data frames arriving on a network interface, comprising the following steps implemented in the network interface: storing a set of target positions (tgtPOS), positions in a frame at which are expected at least one parameter characterizing a subframe (ETH_TYPE) and parameters (SRC_IP, DST_IP) characterizing a client-server session; storing an expected value (xpVAL) for the subframe parameter; receiving a current frame and comparing the value (xtVAL) received at the position of the subframe parameter to the expected value; if equal, calculating an index (IDX) from the values received at the positions of the session parameters; and routing the current frame to a processing resource associated with the index.

Abstract: The invention relates to the pseudo-dynamic routing in a cluster comprising nodes, of the static communication links connecting these nodes. The routing is based on load levels associated with the links. After having received (635) a list of node identifiers, these identifiers designating a set of nodes allotted to the execution of a task, a weight having a first predetermined value is assigned (655) to a pair formed of an identifier of a first and of a second node of said set of nodes, the first and second nodes being distinct, a weight having a second predetermined value, distinct from the first value, being assigned by default to the formed pairs of identifiers of nodes allotted to different tasks. The cluster is then routed, the routing comprising the selecting (610) of a route between the first and second nodes and the incrementing (625) of a load level associated with each link comprising the selected route of the first value.

Abstract: The invention relates in particular to a computer system including peripheral devices (600) and at least one switch (605) connected to each device. A first device includes a means for initiating a control of direct access to memory areas, each one of which is associated with a separate element of the system. The switch includes a means for transmitting at least a portion of the control to each element. At least one element comprises a second device including a means for receiving at least one control of direct access to a memory area of said second device, said control being received from said first device via said switch, and a means for transmitting said received control to a component of said second device. Said system allows said first device to perform a direct data transfer to or from a memory of said first peripheral device from or to each element.

Abstract: The subject of the invention is in particular the direct transfer of data between first and second peripherals connected via a communication bus. For this purpose, the first peripheral comprises a controller for direct access to a memory having means (425) for initiating at least one command for direct access to a region of a memory external to said first peripheral and means (400) for receiving at least one command for direct access to a region of a memory of said first peripheral, said command being received from said at least one second peripheral, and means (415) for transmitting said at least one received direct access command to a component of said first peripheral. The controller thus allows a controller of direct access to a memory of said at least one second peripheral to carry out a direct transfer of at least one data item to or from a memory of said first peripheral from or to said second peripheral.

Abstract: A system comprising a peripheral having a timing mechanism and a node, one of which comprises a real memory space and the other a corresponding virtual memory space, is disclosed. On receiving a timing command in the real memory space, comprising references to an event and time, an entry comprising data relative to the event and time references is created in a monitoring queue of the peripheral. A current point in time is then compared, in the peripheral, to a scheduled point in time linked to an item of data relative to a time reference stored in the monitoring queue. In response, if the current point in time is after the scheduled point in time, an item of data relative to a reference linked to the item of data relative to a time reference stored in the monitoring queue is stored in the real memory space.

Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.

Abstract: The invention relates to the pseudo-dynamic routing in a cluster comprising nodes, of the static communication links connecting these nodes. The routing is based on load levels associated with the links After having received (635) a list of node identifiers, these identifiers designating a set of nodes allotted to the execution of a task, a weight having a first predetermined value is assigned (655) to a pair formed of an identifier of a first and of a second node of said set of nodes, the first and second nodes being distinct, a weight having a second predetermined value, distinct from the first value, being assigned by default to the formed pairs of identifiers of nodes allotted to different tasks. The cluster is then routed, the routing comprising the selecting (610) of a route between the first and second nodes and the incrementing (625) of a load level associated with each link comprising the selected route of the first value.

Abstract: The invention relates in particular to the optimization of routing in a cluster comprising a plurality of nodes and static communication links connecting nodes of the plurality of nodes, said routing being based on load levels associated with the communication links. In order to establish a connection between at least two nodes of the cluster that have been identified (505), at least one route is determined (510) that connects the identified nodes according to the communication links, said route being determined according to the nodes identified, communication links and at least one load level associated with each communication link. A determined route is selected. Subsequently, a value of weight associated with the selected route is estimated (520) and a load level associated with each communication link of the selected route is incremented (525).

Abstract: The subject of the invention is in particular the direct transfer of data between first and second peripherals connected via a communication bus. For this purpose, the first peripheral comprises a controller for direct access to a memory having means (425) for initiating at least one command for direct access to a region of a memory external to said first peripheral and means (400) for receiving at least one command for direct access to a region of a memory of said first peripheral, said command being received from said at least one second peripheral, and means (415) for transmitting said at least one received direct access command to a component of said first peripheral. The controller thus allows a controller of direct access to a memory of said at least one second peripheral to carry out a direct transfer of at least one data item to or from a memory of said first peripheral from or to said second peripheral.

Abstract: The invention relates in particular to a computer system including peripheral devices (600) and at least one switch (605) connected to each device. A first device includes a means for initiating a control of direct access to memory areas, each one of which is associated with a separate element of the system. The switch includes a means for transmitting at least a portion of the control to each element. At least one element comprises a second device including a means for receiving at least one control of direct access to a memory area of said second device, said control being received from said first device via said switch, and a means for transmitting said received control to a component of said second device. Said system allows said first device to perform a direct data transfer to or from a memory of said first peripheral device from or to each element.