Abstract: A device including first and second chips, the first chip including an electronic circuit and the second chip including a capacitor having a density greater than 700 nF/mm{circumflex over (?)}2, the first and second chips being bonded to each other by molecular bonding.

Abstract: An interposer including capacitors having a density greater than 700 nF/mm{circumflex over (?)}2. advantageously greater than 1 ?F/mm{circumflex over (?)}2. the interposer being adapted to being bonded to a chip by hybrid bonding.

Abstract: A semiconductor on insulator type substrate, comprising at least: a support layer; a semiconductor surface layer; a buried dielectric layer located between the support layer and the semiconductor surface layer; a trap rich layer located between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and/or a phase change material; in which the trap rich layer comprises at least one first region and at least one second region adjacent to each other in the plane of the trap rich layer, the material of the at least one first region being in an at least partially recrystallized state and having an electrical resistivity less than that of the material in the at least one second region.

Abstract: A semiconductor on insulator type substrate, comprising at least: a support layer; a semiconductor surface layer; a buried dielectric layer located between the support layer and the semiconductor surface layer; a trap rich layer located between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and/or a phase change material; in which the trap rich layer comprises at least one first region and at least one second region adjacent to each other in the plane of the trap rich layer, the material of the at least one first region being in an at least partially recrystallized state and having an electrical resistivity less than that of the material in the at least one second region.

Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.

Abstract: A TSV via structure comprising an upper part made on the side of the front face of a substrate in which electronic components are located and a lower part with height and cross-section smaller than the height and cross-section the upper part, the arrangement of the connection element in the substrate being such that it releases stresses generated by the different materials of said structure.

Abstract: RF transmission device including at least: a substrate comprising first and second faces opposite to each other; a first RF transmission electronic circuit arranged on and/or in the substrate; a first antenna arranged on the side of the first face of the substrate, spaced apart from the first face of the substrate and electrically connected to the first RF transmission electronic circuit; a first electromagnetic wave reflector coupled to the first antenna and including: a first high impedance surface comprising at least several first electrically conducting elements forming a first periodic structure and arranged on the first face of the substrate opposite the first antenna; a first electrically conducting ground plane arranged at least partially opposite the first antenna.

Abstract: An electronic chip including an integrated circuit arranged a face of a substrate, and a protection device arranged partially facing the integrated circuit is provided. The protection device includes a capacitor having a first electrode and a second electrode between which a layer of phase change material is disposed changing locally from a first resistive state to a second resistive state different from the first state by penetration of a beam. The first state is an amorphous state wherein the capacitor has a first capacitance and/or a first resistance and the second state is a crystalline state wherein the capacitor has a second capacitance and/or a second resistance different from the first capacitance and first resistance. The protection device is electrically connected to the integrated circuit by at least one of the first or second electrodes so that the integrated circuit measures the resistance and/or capacitance of the capacitor.

Abstract: An electronic chip is provided, including an electronic circuit located at a front face of a substrate; a capacitive element placed at a back face of the substrate and facing the electronic circuit, and electrically connected to the electronic circuit by a first electrical connection and a second electrical connection, the first electrical connection including at least a first electrically conducting via passing through the substrate, the electronic circuit being configured to measure a value of electrical capacitance of the capacitive element between the first and the second electrical connections; and a plurality of second vias or trenches passing through the back face of the substrate and a part of the thickness of the substrate, and extending toward the electronic circuit such that bottom walls of the plurality of second vias or trenches are separated from the electronic circuit by at least one non-zero distance.

Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.

Abstract: Electronic chip comprising: an electronic circuit located at a front face of a substrate; a capacitive element placed at a back face of the substrate and facing the electronic circuit, and electrically connected to the electronic circuit by a first electrical connection and a second electrical connection, the first electrical connection including at least a first electrically conducting via passing through the substrate, the electronic circuit being capable of measuring the value of the electrical capacitance of the capacitive element between the first and the second electronic connections, and at least one second via or a trench passing through the back face of the substrate and a part of the thickness of the substrate, and facing the electronic circuit such that a bottom wall of the second via or of the trench are separated from the electronic circuit by a non-zero distance.

Abstract: A variety of circuits, methods and devices are implemented for radiofrequency amplifiers. According to one such implementation, a radiofrequency amplifier circuit is implemented in a SMD package. The circuit amplifies a radiofrequency signal having a base-band portion and a plurality of carrier signals frequency-spaced larger than the base-band bandwidth. The circuit includes a radiofrequency transistor connected to a circuit output having a parasitic output capacitance. The source-drain terminal is electrically connected to the circuit output. An internal shunt inductor provides compensation for the parasitic output capacitance. A high-density capacitor is connected between the internal shunt inductor and a circuit ground. The high-density capacitor has a terminal with a surface area can be at least ten times that of a corresponding planar surface.

Abstract: A variety of circuits, methods and devices are implemented for radiofrequency amplifiers. According to one such implementation, a radiofrequency amplifier circuit is implemented in a SMD package. The circuit amplifies a radiofrequency signal having a base-band portion and a plurality of carrier signals frequency-spaced larger than the base-band bandwidth. The circuit includes a radiofrequency transistor connected to a circuit output having a parasitic output capacitance. The source-drain terminal is electrically connected to the circuit output. An internal shunt inductor provides compensation for the parasitic output capacitance. A high-density capacitor is connected between the internal shunt inductor and a circuit ground. The high-density capacitor has a terminal with a surface area can be at least ten times that of a corresponding planar surface.

Abstract: The integrated microelectronics component comprises an electric conductor forming a transmission line element for a radio frequency electromagnetic wave. This electric conductor is surrounded at least partially by a preferably closed magnetic circuit, formed at least by superposition of a layer of ferromagnetic material having a saturation magnetization value greater than or equal to 800 kA/m and of a layer of magnetic material. The layer of magnetic material then generates a uniaxial magnetic anisotropy in the adjacent ferromagnetic layer. A high magnetization can then be combined with a high anisotropy, thus enabling operation in high frequency ranges, for example about 5 to 20 GHz.

Abstract: The integrated microelectronics component comprises an electric conductor forming a transmission line element for a radio frequency electromagnetic wave. This electric conductor is surrounded at least partially by a preferably closed magnetic circuit, formed at least by superposition of a layer of ferromagnetic material having a saturation magnetization value greater than or equal to 800 kA/m and of a layer of magnetic material. The layer of magnetic material then generates a uniaxial magnetic anisotropy in the adjacent ferromagnetic layer. A high magnetization can then be combined with a high anisotropy, thus enabling operation in high frequency ranges, for example about 5 to 20 GHz.