Abstract: Systems and methods are disclosed for secure control flow prediction. Some implementations may be used to eliminate or mitigate the Spectre-class of attacks in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions may include a control flow predictor with entries that include branch target addresses associated with instructions. The branch target addresses may be predictions. A context tag associated with an entry may be compared to a context identifier associated with a currently executing process. Responsive to a mismatch between the context tag and the context identifier, the control flow predictor may provide an alternate value in place of a branch target address.

Abstract: Systems and methods are disclosed for secure debug architecture. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions; a debug interface comprising two or more conductors with input/output drivers configured to, when enabled, transmit and receive signals between the processor core and an external host device via the two or more conductors; and wherein the integrated circuit is configured to: receive a request from a host device for access to the integrated circuit via the debug interface; responsive to the request, generate a random number; transmit the random number from the integrated circuit to the host device via the debug interface; receive, from the host device via the debug interface, input data that has been encrypted using the random number as a key; and decrypt the input data using the random number as a key.

Abstract: Systems and methods are disclosed for secure debug architecture. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions; a debug interface comprising two or more conductors with input/output drivers configured to, when enabled, transmit and receive signals between the processor core and an external host device via the two or more conductors; and wherein the integrated circuit is configured to: receive a request from a host device for access to the integrated circuit via the debug interface; responsive to the request, generate a random number; transmit the random number from the integrated circuit to the host device via the debug interface; receive, from the host device via the debug interface, input data that has been encrypted using the random number as a key; and decrypt the input data using the random number as a key.

Abstract: The invention relates to methods of interleaving payload data and integrity control data in an external memory interfaced with a microcontroller to improve data integrity check, enhance data confidentiality and save internal memory. Data words are received for storing in the external memory. Each data word is used to generate a respective integrity word, while an associated logic address is translated to two physical addresses in the external memory, one for the data word and the other for the integrity word. The two physical addresses for the data and integrity words are interleaved in the external memory, and sometimes, in a periodic scheme. In particular, each data word may be associated to an integrity sub-word included in an integrity word having the same length with that of a data word. The external memory may have dedicated regions for the data words and the integrity words, respectively.

Abstract: A tamper resistant keypad includes one or more key assemblies having a resilient key member and a contact. The resilient key member is configured to flex when the key assembly is depressed to allow the contact to close a key press detection circuit on a circuit board to register a key press. A tamper detection switch assembly at least partially surrounds the resilient key member. The tamper detection switch assembly is configured to detect attempts to access the key assembly.

Abstract: A tamper resistant keypad includes one or more key assemblies having a resilient key member and a contact. The resilient key member is configured to flex when the key assembly is depressed to allow the contact to close a key press detection circuit on a circuit board to register a key press. A tamper detection switch assembly at least partially surrounds the resilient key member. The tamper detection switch assembly is configured to detect attempts to access the key assembly.

Abstract: The invention relates to methods of interleaving payload data and integrity control data in an external memory interfaced with a microcontroller to improve data integrity check, enhance data confidentiality and save internal memory. Data words and are received for storing in the external memory. Each data word is used to generate a respective integrity word, while an associated logic address is translated to two physical addresses in the external memory, one for the data word and the other for the integrity word. The two physical addresses for the data and integrity words are interleaved in the external memory, and sometimes, in a periodic scheme. In particular, each data word may be associated to an integrity sub-word included in an integrity word having the same length with that of a data word. The external memory may have dedicated regions for the data words and the integrity words, respectively.

Abstract: A tamper resistant keypad includes one or more key assemblies having a resilient key member and a contact. The resilient key member is configured to flex when the key assembly is depressed to allow the contact to close a key press detection circuit on a circuit board to register a key press. A tamper detection switch assembly at least partially surrounds the resilient key member. The tamper detection switch assembly is configured to detect attempts to access the key assembly.

Abstract: A method and device are disclosed for executing applications that involve secure transactions and or conditional access to valuable contents and/or services. The device includes an integrated circuit that has a central processing unit, an internal memory, input/output connections for external memory and connection ports for an external interface circuit incorporated on a single chip. The internal memory includes a secured memory area accessible to the central processing unit only. The secret memory area contains a secret encryption key used for encryption of sensitive data stored in the extenal memory. Preferably, the chip includes a random number generator. A hash value is obtained from a random number generated by the random number generator, the random number with its hash value are encrypted with the secret key, and the encrypted random number with its hash value are stored in the external memory. As a result, the device has a chip that is uniquely paired with the external memory.

Abstract: The invention concerns a method for local recording of digital data received by a transmission network, which consists in encrypting the digital data received with a local recording key (KLEA) and in locally storing the encrypted data (7). The method is characterized in that it comprises the following steps: generating a content key (CK), combining the content key (CK) and a base key (BK) to obtain the local recording key (KLEA), storing the content key (CK) and the encrypted data (7) together with the local recording key (KLEA). The invention is particularly applicable to local recording of digital data derived from digital television broadcasting.

Abstract: For transmitting confidential data, two devices (D1, D2) are linked through a transmission channel which is secured by symmetric encryption with a shared secret session key.