Patents by Inventor Yann Ruet

Yann Ruet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11527608
    Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: December 13, 2022
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Franz Hirler, Wolfgang Jantscher, Yann Ruet, Armin Willmeroth
  • Publication number: 20210193796
    Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Franz Hirler, Wolfgang Jantscher, Yann Ruet, Armin Willmeroth
  • Patent number: 10971582
    Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Franz Hirler, Wolfgang Jantscher, Yann Ruet, Armin Willmeroth
  • Publication number: 20200044019
    Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.
    Type: Application
    Filed: July 24, 2019
    Publication date: February 6, 2020
    Inventors: Franz Hirler, Wolfgang Jantscher, Yann Ruet, Armin Willmeroth
  • Patent number: 10354992
    Abstract: A semiconductor device includes a transistor arrangement and a diode structure. The diode structure is coupled between a gate electrode structure of the transistor arrangement and a source electrode structure of the transistor arrangement. An insulating layer is located vertically between the diode structure and a front side surface of a semiconductor substrate of the semiconductor device. The diode structure includes at least one diode pn-junction. A substrate pn-junction extends from the front side surface of the semiconductor substrate into the semiconductor substrate between a shielding doping region and an edge doping portion. The edge doping portion is located adjacent to the shielding doping region within the semiconductor substrate. At the front side surface of the semiconductor substrate, the substrate pn-junction is located laterally between the diode pn-junction and a source contact region of the diode structure with the source electrode structure.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Joachim Weyers, Franz Hirler, Ahmed Mahmoud, Yann Ruet, Enrique Vecino Vazquez
  • Publication number: 20180090479
    Abstract: A semiconductor device includes a transistor arrangement and a diode structure. The diode structure is coupled between a gate electrode structure of the transistor arrangement and a source electrode structure of the transistor arrangement. An insulating layer is located vertically between the diode structure and a front side surface of a semiconductor substrate of the semiconductor device. The diode structure includes at least one diode pn-junction. A substrate pn-j unction extends from the front side surface of the semiconductor substrate into the semiconductor substrate between a shielding doping region and an edge doping portion. The edge doping portion is located adjacent to the shielding doping region within the semiconductor substrate. At the front side surface of the semiconductor substrate, the substrate pn-junction is located laterally between the diode pn-junction and a source contact region of the diode structure with the source electrode structure.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 29, 2018
    Inventors: Joachim Weyers, Franz Hirler, Ahmed Mahmoud, Yann Ruet, Enrique Vecino Vazquez