Patents by Inventor Yann Tellier

Yann Tellier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delay circuit with accurate time to frequency conversion
    Patent number: 7355465
    Abstract: A delay circuit comprises a signal generator and a delay component. The signal generator comprises a terminal for receiving a trigger signal and an output for outputting a signal when receiving a trigger signal with a pre-determined characteristic. The delay mean comprises an input for receiving the signal outputted by the signal generator and an output for generating a signal delayed with a delay referred to the time the delay mean received the signal outputted by the signal generator.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: April 8, 2008
    Assignee: Infineon Technologies AG
    Inventors: Vincent Gouin, Yann Tellier
  • Apparatus for determining the access time and/or the minimally allowable cycle time of a memory
    Patent number: 7171611
    Abstract: An apparatus for determining the access time and the minimally allowable cycle time of a memory, comprising a clock for generating a signal which stimulates memory data output, programmable delay means for generating a delayed signal, sample-and-hold means for sampling the data output of the memory in response to the delayed signal, a comparator for comparing the sampled data to reference values, and a test status generator, wherein the test status depends on the results of more than one of the comparisons.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: January 30, 2007
    Assignee: Infineon Technologies AG
    Inventors: Vincent Gouin, Simone Borr, Yann Tellier
  • Delay circuit with accurate time to frequency conversion
    Publication number: 20060076996
    Abstract: A delay circuit comprises a signal generator and a delay component. The signal generator comprises a terminal for receiving a trigger signal and an output for outputting a signal when receiving a trigger signal with a pre-determined characteristic. The delay mean comprises an input for receiving the signal outputted by the signal generator and an output for generating a signal delayed with a delay referred to the time the delay mean received the signal outputted by the signal generator.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 13, 2006
    Inventors: Vincent Gouin, Yann Tellier
  • Apparatus for determining the access time and/or the minimally allowable cycle time of a memory
    Publication number: 20050204211
    Abstract: An apparatus for determining the access time and the minimally allowable cycle time of a memory, comprising a clock for generating a signal which stimulates memory data output, programmable delay means for generating a delayed signal, sample-and-hold means for sampling the data output of the memory in response to the delayed signal, a comparator for comparing the sampled data to reference values, and a test status generator, wherein the test status depends on the results of more than one of the comparisons.
    Type: Application
    Filed: January 14, 2005
    Publication date: September 15, 2005
    Inventors: Vincent Gouin, Simone Borri, Yann Tellier