Abstract: An ESD protection device for a multi-voltage system includes a first circuit block, a second circuit block, a first power clamp circuit and a second power clamp circuit. The first and second circuit blocks respectively operate at a first power voltage and a second power voltage smaller than the first power voltage. The first power clamp circuit, coupled to the first circuit block, has a breakdown voltage between the first and second power voltages and a holding voltage greater than or equal to the first power voltage. The second power clamp circuit is smacked on the first power clamp circuit and coupled to the second circuit block. A total breakdown voltage of the first and second power clamp circuits is greater than the second power voltage, and a total holding voltage of the first and second power clamp circuits is greater than or equal to the second power voltage.

Abstract: An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is located on the first poly-silicon layer to form a capacitor. The second section of the second poly-silicon layer is located on the diffusion layer to form a resistor.

Abstract: A layout structure of an electrostatic discharge protection circuit and a fabrication process thereof are provided. The electrostatic discharge protection circuit includes a substrate, a protection element and a resistor, wherein a part of or all of the area of the resistor is disposed in the region of the protection element, which saves the footprint of the resistor and reduces a junction parasitic capacitance formed in the protection element. Thus, the production cost of the electrostatic discharge protection circuit is reduced, and the influence of the electrostatic discharge protection circuit on the property of the entire internal circuit is minimized.

Abstract: An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is located on the first poly-silicon layer to form a capacitor. The second section of the second poly-silicon layer is located on the diffusion layer to form a resistor.

Abstract: A layout structure of an electrostatic discharge protection circuit and a fabrication process thereof are provided. The electrostatic discharge protection circuit includes a substrate, a protection element and a resistor, wherein a part of or all of the area of the resistor is disposed in the region of the protection element, which saves the footprint of the resistor and reduces a junction parasitic capacitance formed in the protection element. Thus, the production cost of the electrostatic discharge protection circuit is reduced, and the influence of the electrostatic discharge protection circuit on the property of the entire internal circuit is minimized.

Abstract: A differential input/output device including an electro static discharge protection circuit is provided. The differential input/output device includes a P-type differential pair. The P-type differential pair includes two P-type transistors. The gate of each P-type transistor is coupled to an N-type transistor to protect the P-type transistor when CDM ESD occurs. Compared with the conventional technology, the protection device of the present invention provides a lower impedance current path when CDM ESD occurs in the input device.

Abstract: An electrostatic discharge (ESD) protection apparatus for programmable device is provided. This ESD protection device provides a high impedance along the electrical path from the pad to the power system for preventing the programmable device from damages induced by ESD event; and the impedance can be intentionally decreased during the normal reading and writing operations.

Abstract: An electronic static discharge (ESD) protection apparatus for a programmable device is provided. The apparatus can improve the turn-on efficiency and reduce the surface area of the chip efficiently by providing a low impedance current path which can sufficiently lower the voltage of the programmable device when ESD occurs. The ESD protection apparatus includes an ESD protection device, a programmable device, a first circuit, a second circuit, and a third circuit.