Abstract: An arrangement for repairing at least one faulty bit line of a memory includes three multiplexer stages. The memory has a plurality of columns, each column having k memory subcolumns. Each memory subcolumn has n bit lines. The first multiplexer stage has k multiplexers, each multiplexer having a multiplexer output and n multiplexer inputs connected to n bitlines of a memory subcolumn. The multiplexers of the first multiplexer stage are switched in response to a first address decoding signal. The second multiplexer stage has k multiplexers, each second stage multiplexer having a first multiplexer input connected to a multiplexer output of a first stage multiplexer associated with a first memory subcolumn, a second multiplexer input connected to a multiplexer output of a first stage multiplexer associated with a second memory subcolumn, and a multiplexer output. The multiplexers of the second multiplexer stage are switched in response to a fuse data signal.

Abstract: An arrangement for repairing at least one faulty bit line of a memory includes three multiplexer stages. The memory has a plurality of columns, each column having k memory subcolumns. Each memory subcolumn has n bit lines. The first multiplexer stage has k multiplexers, each multiplexer having a multiplexer output and n multiplexer inputs connected to n bitlines of a memory subcolumn. The multiplexers of the first multiplexer stage are switched in response to a first address decoding signal. The second multiplexer stage has k multiplexers, each second stage multiplexer having a first multiplexer input connected to a multiplexer output of a first stage multiplexer associated with a first memory subcolumn, a second multiplexer input connected to a multiplexer output of a first stage multiplexer associated with a second memory subcolumn, and a multiplexer output. The multiplexers of the second multiplexer stage are switched in response to a fuse data signal.