Abstract: A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path, said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open.

Abstract: An overlayer intended to cover an object in order to detect a defect on a surface of the object, comprises an assembly made up of a plurality of current-conducting wire elements of different mechanical resistances and a means for insulating the conducting wire elements, each conducting wire element being arranged such as to at least partially cover a surface of the object when the overlayer covers the object, each conducting wire element being arranged to allow the connection thereof to a test device for detecting a defect affecting the conducting element.

Abstract: A method for online testing pipeline systems comprising a succession of stages separated by buffers each associated with an idle signal, or idle signal, and/or at least one status bit, comprising: detecting values of the idle signal and/or the corresponding status bits indicating the availability of a cycle or the abrupt interruption of the flow of operations in a pipeline, and indicating that a valid operation, executed by a stage in the pipeline, is followed by an unused cycle; maintaining the state of the buffer in order to allow said valid operation to be re-executed during the unused cycle indicated by said idle signal; re-executing, during the unused cycle, the valid operation, in order to obtain at least a first version and a second version of said valid operation; memorizing, at the output of the pipeline, the results that correspond to the first version of said repeated or re-executed operation, in order to compare with the results of said second version of the same repeated or re-executed operation;

Abstract: A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open.

Abstract: A method for online testing pipeline systems comprising a succession of stages separated by buffers each associated with an idle signal, or idle signal, and/or at least one status bit, comprising: detecting values of the idle signal and/or the corresponding status bits indicating the availability of a cycle or the abrupt interruption of the flow of operations in a pipeline, and indicating that a valid operation, executed by a stage in the pipeline, is followed by an unused cycle; maintaining the state of the buffer in order to allow said valid operation to be re-executed during the unused cycle indicated by said idle signal; re-executing, during the unused cycle, the valid operation, in order to obtain at least a first version and a second version of said valid operation; memorizing, at the output of the pipeline, the results that correspond to the first version of said repeated or re-executed operation, in order to compare with the results of said second version of the same repeated or re-executed operation;

Abstract: A method for detecting and determining a position of faults using reflectometry in a wired electrical network including: injecting a test signal e(t) into a cable in the electrical network, a timing of successive injections being controlled by a synchronization module that generates an emission clock signal and a reception clock signal; retrieving a reflected signal on the cable; sampling the reflected signal at a frequency Fe=1/Te, where Te is a sampling period; counting a number of samples obtained for the reflected signal and comparing the number of samples obtained with a number n predefined as a function of a length of the cable or the electrical network to be diagnosed, where n is an integer; repeating the injecting, the sampling, and the counting steps N times, shifting the emission clock signal by a duration ?; reconstituting the reflected signal from n*N samples obtained; and analyzing the reconstituted reflected signal to detect a fault.

Abstract: A method for protecting digital memory against permanent and transient errors and a related device, the digital data being stored in at least one storage matrix of memory cells in a given number of rows and columns, comprises: an encoding step generating code words from data organized in binary words by application of asymmetric code introducing at least two different levels of protection, the first level of protection said to be high being associated with a first sub-group of bits of the code word and a second level of protection said to be low being associated with a second sub-group of the same word; swapping positions of the bits of the code word making the bits with a high level of protection correspond for their storage to the columns of the storage area comprising defective memory cells and the bits with a low level of protection to the remaining columns.

Abstract: This invention relates to a method for detecting and determining the position of faults using reflectometry in a wired electrical network comprising the following steps: inject a test signal into a cable in said network, retrieve a reflected signal on said cable, sample said reflected signal at a frequency Fe=1/Te, repeat the previous steps N times, where N is an integer number, for each injected test signal, retrieve n samples from the corresponding reflected signal, where n is an integer number, analyse M=n*N retrieved samples to detect and locate a fault in the wired electrical network. The method is characterised in that the retrieved samples are compared with an adaptive threshold defined for each diagnostic as a function of the test signal injected in the tested cable.

Abstract: The present invention relates to a parametric scan register and a method of testing a digital circuit with the aid of such a register. The parametric scan register includes a memory cell having at least one data input, able to receive a test datum, and transferring to its output a representative signal indicative of the test datum by use of a synchronization signal. It furthermore includes a parametric test block one input of which is linked to the output (s) of the cell, the output signal of the cell being transferred at the output of the parametric test block through an internal module, this internal module operating according to modes able to modify the output signal of the cell. Embodiments of the invention apply to the testing of integrated circuits with high integration density, for example in the field of nanotechnologies.

Abstract: The invention relates to a method and a device for analyzing electric cable networks in order to detect and locate defects in the cables comprising at least one branch connection from which N secondary sections extend. The method involves injecting into the network, at a plurality of injection points E, pseudo-random sequences of digital signals PNi(t) that are de-correlated from each other, and collecting, at one or more observation points Sj, composite time signals Rj(t) generated by the circulation of the output sequences and the reflections thereof in the impedance discontinuities of the network. The correlation between the composite signals and the time-offset pseudo-random sequences is then computed, and the positions of correlation peaks are sought to deduce therefrom the positions of defects in the network by taking into account the signal propagation speed in the network.