Abstract: An integrated circuit includes an electrostatic discharge (ESD) detection circuit which detects an ESD event and generates an event signal. In response to that event signal, a control circuit controls the operation of a buffer circuit to function in an additional mode wherein the normal differential operation of the buffer circuit is disabled and the buffer circuit is instead configured to form a conduction path between supply rails to discharge the ESD event. Preferably, a plurality of buffer circuits are driven in parallel by the control circuit to function in the additional mode to form parallel discharge paths for the ESD event. Multiple ESD detection circuits may be provided, and any one of those detection circuits can trigger the control circuitry to place all of the buffer circuits in the additional mode.

Abstract: A digital to analog converter (DAC) circuit operates over an upper range and a lower range. An upper voltage node is designated AVDD; a middle voltage node is designated HVDD; and a lower voltage node designated ground. An upper DAC stage has at least one NMOS transistor that produces an output to an upper range output node when the output is in the upper range. A lower DAC stage has at least one PMOS transistor that produces an output to a lower range output node when the output is in the lower range. A body bias control circuit couples the body of the upper NMOS transistor to a voltage source equal to HVDD?Vbe and connects the body of the lower PMOS transistor to voltage source equal to HVDD+Vbe.

Abstract: A method for controlling a piezoelectric motor, such that control signals of the motor are periodic non-sinusoidal voltage signals.

Abstract: In one embodiment consistent with the present invention, a digital to analog converter (DAC) circuit operates over an upper range and a lower range. An upper voltage node is designated AVDD; a middle voltage node is designated HVDD; and a lower voltage node designated ground. An upper DAC stage has at least one NMOS transistors that produces an output to an upper range output node when the output is in the upper range. A lower DAC stage has at least one PMOS transistors that produces an output to a lower range output node when the output is in the lower range. A body bias control circuit couples the body of the upper NMOS transistor to a voltage source equal to HVDD?Vbe and connects the body of the lower PMOS transistor to voltage source equal to HVDD+Vbe. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A low drop-out DC voltage regulator regulates a voltage from a DC supply and includes: a pass device controllable to maintain a voltage at an output of the regulator and arranged to provide a first current from the DC supply, at least part of said first current being provided to a load coupled to the output of the regulator; and a current regulator coupled to said pass device and to the output of the regulator. The current regulator is arranged to conduct a second current controllable such that the first current through said pass device remains constant irrespective of variations in a load current to said load.

Abstract: A method for controlling a piezoelectric motor, such that control signals of the motor are periodic non-sinusoidal voltage signals.

Abstract: A bootstrap driver comprises an output stage having an N-type high-side transistor and a low-side transistor, also of the N-type, which are arranged in series between a positive supply terminal and a negative supply terminal. A control circuit of the high-side transistor and a control circuit of the low-side transistor are respectively supplied by a first voltage regulator and a second voltage regulator, which are mutually independent. A recovery diode is connected by its anode to the output of the first voltage regulator and by its cathode to the positive supply terminal, in order to conduct the reverse current of a bootstrap diode when the output of the circuit switches from a low state to a high state.

Abstract: A bootstrap driver comprises an output stage having an N-type high-side transistor and a low-side transistor, also of the N-type, which are arranged in series between a positive supply terminal and a negative supply terminal. A control circuit of the high-side transistor and a control circuit of the low-side transistor are respectively supplied by a first voltage regulator and a second voltage regulator, which are mutually independent. A recovery diode is connected by its anode to the output of the first voltage regulator and by its cathode to the positive supply terminal, in order to conduct the reverse current of a bootstrap diode when the output of the circuit switches from a low state to a high state.

Abstract: An intermediate stage of a high-voltage inverting amplifier includes a drive transistor (MB5) of the thin-gate-oxide high-voltage MOS type connected between a supply terminal and the gate of an output transistor (M28). At least one first diode (DB) is included in the intermediate stage, wherein the cathode of that diode is connected to the gate of the drive transistor and the anode is connected to a level transposition stage of the amplifier. A control circuit is connected to the gate of the drive transistor so as to enable it to conduct when an initially zero supply voltage reaches the threshold voltage of the drive transistor. This causes the output transistor to conduct more quickly with increased supply voltage than would be experienced with prior art designs.

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract: An intermediate stage of a high-voltage inverting amplifier includes a drive transistor (MB5) of the thin-gate-oxide high-voltage MOS type connected between a supply terminal and the gate of an output transistor (M28). At least one first diode (DB) is included in the intermediate stage, wherein the cathode of that diode is connected to the gate of the drive transistor and the anode is connected to a level transposition stage of the amplifier. A control circuit is connected to the gate of the drive transistor so as to enable it to conduct when an initially zero supply voltage reaches the threshold voltage of the drive transistor. This causes the output transistor to conduct more quickly with increased supply voltage than would be experienced with prior art designs.

Abstract: Disclosed is a device to control a circuit for the vertical deflection of a spot scanning a screen, and more particularly a control device whose output amplifier stage works in class D mode at the rate of a switching signal called a first switching signal. The control device has an internal auxiliary supply to generate the overvoltage needed for the fast flyback of the spot. This auxiliary power supply is a switching voltage generation circuit whose switching signal, called a second switching signal, is synchronous with the first switching signal. The present invention has been shown to used advantageously in television screens and/or computer screens.

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract: Disclosed is a device to control a circuit for the vertical deflection of a spot scanning a screen, and more particularly a control device whose output amplifier stage works in class D mode at the rate of a switching signal called a first switching signal. The control device has an internal auxiliary supply to generate the overvoltage needed for the fast flyback of the spot. This auxiliary power supply is a switching voltage generation circuit whose switching signal, called a second switching signal, is synchronous with the first switching signal. The present invention has been shown to used advantageously in television screens and/or computer screens.

Abstract: The control device includes an output amplifier stage ETS supplied by a main supply for controlling the vertical scan of the spot, and an auxiliary supply capable of delivering an overvoltage and a first two-way switch connected to the output stage and controllable to allow the overvoltage to be delivered to the vertical deflection circuit for flyback of the spot. The output stage is a stage having at least two transistors which are capable of operating in alternating switching mode, at least for control of the vertical scan of the spot, this stage being associated with a smoothing filter connected to the common terminal of the two transistors. The device includes a second two-way switch connected between a first transistor of the output stage and a first terminal of the main supply and controllable to prevent delivery of the overvoltage during control of the vertical scan of the spot.

Abstract: Electronic circuit comprising a first and a second current mirrors, an upstream active element arranged between an input of the first current mirror and an input of the second current mirror, each current mirror being provided with an output. The circuit comprises a first current source arranged in parallel with the input of the first current mirror and a second current source arranged in parallel with the input of the second current mirror, so that the current delivered to the active element is equal to the output current of each current mirror and that the input current of each current mirror is less than the current delivered to the active element by the input of each current mirror and by the associated current source.