Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract: A transistor includes an active layer forming a channel for the transistor, an insulating layer disposed facing a lower face of the active layer, a gate turned toward an upper face of the active layer and a source and a drain disposed on both sides of the gate. At least one among the source and the drain extends at least partly through the active layer and into the insulating layer.

Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal.

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract: A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.

Abstract: The present invention relates to a method for chemically treating the surface condition of a silicon substrate for the roughness contrast characterized in that it comprises at least two successive treatment cycles, with each treatment cycle comprising a first step including placing in contact the silicon substrate with a first solution containing water diluted hydrofluoric (HF) acid and then a second step carried out at a temperature of less than 40° C., comprising placing in contact the silicon layer with a second solution containing water (H2O) diluted ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2), in order to obtain a roughness of less than 0.100 nanometer on a 1 ?m×1 ?m area upon completion of the treatment cycles. The invention will be applied in the field of microelectronics for the production of transistors, of surfaces for photovoltaic panels or for direct molecular bonding.

Abstract: The invention relates to a method for making a semiconducting structure, including: a) forming, on the surface of a semiconductor substrate (2), called the final substrate, a semiconducting layer (4), doped with elements from columns III and V of the Periodic Table so as to form a ground plane, b) forming a dielectric layer (3), c) then assembling, by direct adhesion of the source substrate, on the final substrate (2), the layer (4) forming the ground plane between the final substrate and the source substrate, the dielectric layer being between the source substrate and the ground plane, d) then thinning the source substrate, leaving, on the surface of the semiconductor structure, a film (20) made from a semiconducting material.

Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal.

Abstract: The present invention relates to a method for manufacturing a semiconductor device by wet-process chemical etching, the device comprising at least one layer of silicon (Si) and at least one layer of silicon-germanium (SiGe) and at least one layer of photosensitive resin forming a mask partly covering the layer of silicon-germanium (SiGe) and leaving the layer of silicon-germanium uncovered in certain zones, characterized in that it comprises a step of preparation of an etching solution, having a pH between 3 and 6, from hydrofluoric acid (HF), hydrogen peroxide (H2O2), acetic acid (CH3COOH) and ammonia (NH4OH), and a step of stripping of the layer of silicon-germanium (SiGe) at least at the said zones by exposure to the said etching solution. The invention will be applicable for the manufacture of integrated circuits and more precisely of transistors. In particular, for optimization of CMOS transistors of the latest generation.

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal.

Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.