Patents by Inventor Yannick Marc
Yannick Marc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11982726Abstract: Tracer kinetic models are utilized as temporal constraints for highly under-sampled reconstruction of DCE-MRI data. In one embodiment, a method for improving dynamic contrast enhanced imaging. The method includes steps of administering a magnetic resonance contrast agent to a subject and then collecting magnetic resonance contrast agent from the subject. A tracer kinetic model (i.e. eTofts or Patlak) is selected to be applied to the magnetic resonance imaging data. The tracer kinetic model is applied to the magnetic resonance imaging data. Tracer kinetic maps and dynamic images are simultaneously reconstructed and a consistency constraint is applied. The proposed method allows for easy use of different tracer kinetic models in the formulation and estimation of patient-specific arterial input functions jointly with tracer kinetic maps.Type: GrantFiled: April 15, 2019Date of Patent: May 14, 2024Assignee: University of Southern CaliforniaInventors: Krishna S. Nayak, Yannick Bliesener, Yi Guo, Yinghua Zhu, Sajan Goud Lingala, Robert Marc Lebel
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Publication number: 20230233492Abstract: The present invention relates to a pharmaceutical combination comprising (i) firibastat, (ii) a diuretic and (iii) a blocker of the systemic renin-angiotensin system selected from the group consisting of angiotensin I converting enzyme inhibitors (ACEIs) and angiotensin II receptor type 1 (AT1R) antagonists. Said composition is particularly useful for the treatment of hypertension and related diseases and conditions.Type: ApplicationFiled: May 5, 2021Publication date: July 27, 2023Inventors: FABRICE BALAVOINE, CATHERINE LLORENS-CORTES, YANNICK MARC
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Patent number: 11345658Abstract: The present invention relates to compounds, to compositions comprising the same, to methods for preparing the compounds, and the use of these compounds in therapy. In particular, the present invention relates to a compound that is useful in the treatment and prevention of primary and secondary arterial hypertension, ictus, myocardial ischaemia, cardiac and renal insufficiency, myocardial infarction, peripheral vascular disease, diabetic proteinuria, Syndrome X and glaucoma.Type: GrantFiled: March 11, 2020Date of Patent: May 31, 2022Assignees: QUANTUM GENOMICS, INSTITUT NATIONAL DE LA SANTÉ ET DE LA RECHERCHE MÉDICALE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, COLLEGE DE FRANCEInventors: Fabrice Balavoine, Delphine Compere, Mathilde Keck, Yannick Marc, Catherine Llorens-Cortes, Solène E. Boitard
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Publication number: 20220041548Abstract: The present invention relates to compounds, to compositions comprising the same, to methods for preparing the compounds, and the use of these compounds in therapy. In particular, the present invention relates to a compound that is useful in the treatment and prevention of primary and secondary arterial hypertension, ictus, myocardial ischaemia, cardiac and renal insufficiency, myocardial infarction, peripheral vascular disease, diabetic proteinuria, Syndrome X and glaucoma.Type: ApplicationFiled: March 11, 2020Publication date: February 10, 2022Inventors: FABRICE BALAVOINE, DELPHINE COMPERE, MATHILDE KECK, YANNICK MARC, CATHERINE LLORENS-CORTES, SOLÈNE E. BOITARD
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Patent number: 11192907Abstract: The present invention relates to a novel compound, to a composition comprising the same, to methods for preparing the compound, and the use of this compound in therapy. In particular, the present invention relates to a compound that is useful in the treatment and prevention of primary and secondary arterial hypertension, ictus, myocardial ischaemia, cardiac and renal insufficiency, myocardial infarction, peripheral vascular disease, diabetic proteinuria, Syndrome X and glaucoma.Type: GrantFiled: October 25, 2019Date of Patent: December 7, 2021Assignees: QUANTUM GENOMICS, INSTITUT NATIONAL DE LA SANTÉ ET DE LA RECHERCHE MÉDICALE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, COLLEGE DE FRANCEInventors: Fabrice Balavoine, Delphine Compere, Catherine Llorens-Cortes, Yannick Marc
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Publication number: 20210309678Abstract: The present invention relates to a novel compound, to a composition comprising the same, to methods for preparing the compound, and the use of this compound in therapy. In particular, the present invention relates to a compound that is useful in the treatment and prevention of primary and secondary arterial hypertension, ictus, myocardial ischaemia, cardiac and renal insufficiency, myocardial infarction, peripheral vascular disease, diabetic proteinuria, Syndrome X and glaucoma.Type: ApplicationFiled: October 25, 2019Publication date: October 7, 2021Inventors: FABRICE BALAVOINE, DELPHINE COMPERE, CATHERINE LLORENS-CORTES, YANNICK MARC
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Patent number: 10959938Abstract: The present invention relates to a pharmaceutical composition comprising, in at least one pharmaceutically acceptable support or vehicle, a combination of (3S,3S?)4,4?-disulfanediylbis(3-aminobutane 1-sulfonic acid) or a pharmaceutically acceptable salt or solvate thereof and a second active ingredient selected from the group consisting of angiotensin I converting enzyme inhibitors and angiotensin II receptor type I antagonists. Said composition is particularly useful for the treatment of hypertension and related diseases and conditions.Type: GrantFiled: December 21, 2012Date of Patent: March 30, 2021Assignee: Quantum GenomicsInventors: Catherine Llorens-Cortes, Yannick Marc, Ji Gao-Desliens, Fabrice Balavoine, Lionel Segard
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Patent number: 10558585Abstract: A memory, a data processing system comprising a memory, a method of operating a memory and a memory compiler apparatus and method of memory compilation are provided, which relate to a memory comprising data storage circuitry to store data values at data locations. Addressing circuitry is provided to access the data value at a storage location in dependence on a received address and readout circuitry to provide an output value in dependence on the accessed data value. The memory further comprises scrambling circuitry to select at least one of: a mapping between the address and the storage location; and a mapping between the data value and the output value, in dependence on a received scrambling value. The mapping between the address and the storage location and/or the data value and the output value can thus be easily and rapidly changed.Type: GrantFiled: November 18, 2016Date of Patent: February 11, 2020Assignee: ARM LimitedInventors: Yannick Marc Nevers, Bastien Jean Claude Aghetti, Nicolaas Klarinus Johannes Van Winkelhoff, Stephane Zonza
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Publication number: 20170147509Abstract: A memory, a data processing system comprising a memory, a method of operating a memory and a memory compiler apparatus and method of memory compilation are provided, which relate to a memory comprising data storage circuitry to store data values at data locations. Addressing circuitry is provided to access the data value at a storage location in dependence on a received address and readout circuitry to provide an output value in dependence on the accessed data value. The memory further comprises scrambling circuitry to select at least one of: a mapping between the address and the storage location; and a mapping between the data value and the output value, in dependence on a received scrambling value. The mapping between the address and the storage location and/or the data value and the output value can thus be easily and rapidly changed.Type: ApplicationFiled: November 18, 2016Publication date: May 25, 2017Inventors: Yannick Marc NEVERS, Bastien Jean Claude AGHETTI, Nicolaas Klarinus Johannes VAN WINKELHOFF, Stephane ZONZA
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Publication number: 20150320703Abstract: The present invention relates to a pharmaceutical composition comprising, in at least one pharmaceutically acceptable support or vehicle, a combination of (3S,3S?)4,4?-disulfanediylbis(3-aminobutane 1-sulfonic acid) or a pharmaceutically acceptable salt or solvate thereof and a second active ingredient selected from the group consisting of angiotensin I converting enzyme inhibitors and angiotensin II receptor type I antagonists. Said composition is particularly useful for the treatment of hypertension and related diseases and conditions.Type: ApplicationFiled: December 21, 2012Publication date: November 12, 2015Inventors: Catherine Llorens-Cortes, Yannick Marc, Ji Gao-Desliens, Fabrice Balavoine, Lionel Segard
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Patent number: 8941428Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.Type: GrantFiled: April 9, 2014Date of Patent: January 27, 2015Assignee: ARM LimitedInventors: Virgile Javerliac, Yannick Marc Nevers, Laurent Christian Sibuet, Selma Laabidi
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Publication number: 20140218089Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.Type: ApplicationFiled: April 9, 2014Publication date: August 7, 2014Applicant: ARM LIMITEDInventors: Virgile JAVERLIAC, Yannick Marc NEVERS, Laurent Christian SIBUET, Selma LAABIDI
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Publication number: 20140125392Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: ARM LIMITEDInventors: Virgile JAVERLIAC, Yannick Marc NEVERS, Laurent Christian SIBUET, Selma LAABIDI
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Patent number: 8422262Abstract: A method of generating a ROM bit cell array layout including the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, the memory architecture including a plurality of columns of memory cells, each column of memory cells being located between associated bit lines and virtual ground lines. Adjacent memory cells in each column of memory cells share a common connection to either the associated bit line or the associated virtual ground line. The further steps of evaluating the width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating the layout according to said final width of active area.Type: GrantFiled: April 7, 2011Date of Patent: April 16, 2013Assignee: ARM LimitedInventors: Yannick Marc Nevers, Vincent Philippe Schuppe
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Publication number: 20110249481Abstract: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area.Type: ApplicationFiled: April 7, 2011Publication date: October 13, 2011Applicant: ARM LimitedInventors: Yannick Marc Nevers, Vincent Philippe Schuppe
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Patent number: 7961490Abstract: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area.Type: GrantFiled: January 9, 2009Date of Patent: June 14, 2011Assignee: ARM LimitedInventors: Yannick Marc Nevers, Vincent Philippe Schuppe
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Patent number: 7936578Abstract: A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output lines and a voltage source. The switching device provides an electrical connection between the voltage source and the single one of the three output lines in response to a switching signal, a voltage of the connected output line switching value in response to connection to the predetermined voltage and the multiple bit value represented by the output line is thereby selected. There is also an output device provided for outputting the selected multiple bit value.Type: GrantFiled: August 28, 2009Date of Patent: May 3, 2011Assignee: ARM LimitedInventors: Yannick Marc Nevers, Christophe Denis Lucien Frey, Mikael Brun, Nicolaas Klarinus Johannes van Winkelhoff
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Publication number: 20110051487Abstract: A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output lines and a voltage source. The switching device provides an electrical connection between the voltage source and the single one of the three output lines in response to a switching signal, a voltage of the connected output line switching value in response to connection to the predetermined voltage and the multiple bit value represented by the output line is thereby selected. There is also an output device provided for outputting the selected multiple bit value.Type: ApplicationFiled: August 28, 2009Publication date: March 3, 2011Applicant: ARM LimitedInventors: Yannick Marc Nevers, Christophe Denis Lucien Frey, Mikael Brun, Nicolaas Klarinus Johannes Van Winkelhoff
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Publication number: 20100177544Abstract: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area.Type: ApplicationFiled: January 9, 2009Publication date: July 15, 2010Applicant: ARM LIMITEDInventors: Yannick Marc Nevers, Vincent Philippe Schuppe