Abstract: Provided is a method for performing a plurality of cryptographic operations, that upon reception of a request to perform one of said cryptographic operations, prevents an execution by said processing system of said requested cryptographic operation until a predetermined waiting time (G) has elapsed, and before said predetermined waiting time has elapsed, receives one or more requests to perform another cryptographic operation, and after said predetermined waiting time (G) has elapsed, answers (S3) said requests by executing operations comprising mutualized calculations. The method determines said waiting time depending on execution times of said cryptographic operations to be performed and of said mutualized calculations.

Abstract: Provided is an authentication method, the method comprising sending, by an entity, to a chip, at least one request for getting data; receiving, by the entity, from the chip, data; and, authenticating, by the entity, based on the received data, a family relating to the chip. Other embodiments disclosed.

Abstract: A connected device with at least one sensor adapted to measure at least a physical quantity and to report a measure of this physical quantity to a remote device, the at least one sensor system providing an output Z which is then digitized in order to provide an output signal Y having a first and a second component, the first component being representative of the measured physical quantity X and the second component being representative of the structural noise R introduced by the at least one sensor. The connected device also has a noise generator configured to generate using as an input at least one parameter representative of the structural noise R a blurring noise V which is uncorrelated with said structural noise R; combine the digital output signal Y with the blurring noise V in order to generate a signal Y?; transmit signal Y? to the remote device.

Abstract: Provided is a system on chip comprising a memory controller having a clock synchronization circuitry based on a locked loop. The system on chip further comprises a voltage glitch attack detector configured to monitor a clock synchronization signal generated by the clock synchronization circuitry and check whether the monitored clock synchronization signal is a nominal signal or a signal characteristic of a voltage glitch attack. The voltage glitch attack detector may be a software detector executed by a processing unit. Other embodiments disclosed.

Abstract: A method of detecting a cold-boot attack on an integrated circuit, including the steps of: periodically sampling a signal delivered by at least one ring oscillator; and verifying that the proportion of states “1” and of states “0” of the result of the sampling is within a range of values.

Abstract: A connected device with at least one sensor adapted to measure at least a physical quantity and to report a measure of this physical quantity to a remote device, the at least one sensor system providing an output Z which is then digitized in order to provide an output signal Y having a first and a second component, the first component being representative of the measured physical quantity X and the second component being representative of the structural noise R introduced by the at least one sensor. The connected device also has a noise generator configured to generate using as an input at least one parameter representative of the structural noise R a blurring noise V which is uncorrelated with said structural noise R; combine the digital output signal Y with the blurring noise V in order to generate a signal Y?; transmit signal Y? to the remote device.

Abstract: An electronic system having a processing system with a hardware processor and at least one additional unit the hardware processor having a CPU register and the additional unit having a processing system memory. A secure enclave of the system is configured to monitor the behavior of the processing system and detect a compromise of the processing system. A protection system of the electronic system is configured, upon detection of a compromise of the processing system by the secure enclave, to perform at least one dedicated action on at least one additional unit among the additional units for raising an alert or for applying countermeasures, or on the hardware processor modifying a CPU register of the hardware processor, the protection system and the secure enclave being connected to the additional units.

Abstract: A method for protecting a ciphering algorithm executing looped operations on bits of a first quantity and on a first variable initialized by a second quantity, wherein, for each bit of the first quantity, a random number is added to the state of this bit to update a second variable maintained between two thresholds.

Abstract: A method of protecting a modular exponentiation calculation executed by an electronic circuit using a first register and a second register, successively comprising, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of said other one of the registers is stored in a third register before the first step and is restored in said other one of the registers before the second step.

Abstract: A method of detecting a cold-boot attack includes transferring, into a first volatile memory of an integrated circuit, a pattern stored in a non-volatile memory of the integrated circuit. Power to the non-volatile memory is periodically interrupted and an indication of a number of errors in the non-volatile memory is generated. The indication of the number of errors is compared to one or more thresholds. An occurrence of a cold-boot attack is detected based on the comparison. The pattern may be reloaded into the first volatile memory before each power interruption. The pattern may be selected so that the number of errors varies according to the integrated circuit temperature.

Abstract: A method of verifying the sensitivity of an electronic circuit executing a modular exponentiation calculation in a first register and a second register, successively including, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of that of the first and second registers which contains the multiplier of the operation of the first step is disturbed, for each bit of the exponent, during the execution of the first step.

Abstract: A method of detecting a cold-boot attack includes transferring, into a first volatile memory of an integrated circuit, a pattern stored in a non-volatile memory of the integrated circuit. Power to the non-volatile memory is periodically interrupted and an indication of a number of errors in the non-volatile memory is generated. The indication of the number of errors is compared to one or more thresholds. An occurrence of a cold-boot attack is detected based on the comparison. The pattern may be reloaded into the first volatile memory before each power interruption. The pattern may be selected so that the number of errors varies according to the integrated circuit temperature.

Abstract: A method for detecting a fault injection in a circuit, wherein a bit pattern is mixed in a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mixing.

Abstract: A method of detecting a cold-boot attack on an integrated circuit including the steps of: transferring, into a first volatile memory of the integrated circuit, a pattern stored in a non-volatile memory of the circuit; periodically causing a switching down and a switching up of the first volatile memory; and verifying that the number of bits having switched state is within a range of values.

Abstract: A method for detecting a fault injection in a circuit, wherein a bit pattern is mixed in a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mixing.

Abstract: A method for protecting a ciphering algorithm executing looped operations on bits of a first quantity and on a first variable initialized by a second quantity, wherein, for each bit of the first quantity, a random number is added to the state of this bit to update a second variable maintained between two thresholds.

Abstract: A method of protecting a modular exponentiation calculation executed by an electronic circuit using a first register and a second register, successively comprising, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of said other one of the registers is stored in a third register before the first step and is restored in said other one of the registers before the second step.

Abstract: A method of verifying the sensitivity of an electronic circuit executing a modular exponentiation calculation in a first register and a second register, successively including, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of that of the first and second registers which contains the multiplier of the operation of the first step is disturbed, for each bit of the exponent, during the execution of the first step.

Abstract: A method for detecting a fault injection in a random number generation circuit, wherein a bit pattern is mixed to a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mix.

Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.