Patents by Inventor Yannis Papananos
Yannis Papananos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10069662Abstract: A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.Type: GrantFiled: November 10, 2015Date of Patent: September 4, 2018Assignee: Infineon Technologies AGInventors: Yannis Papananos, David Seebacher, Nikolaos Alexiou, Franz Dielacher, Konstantinos Galanopoulos, Peter Singerl, Marc Tiebout
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Patent number: 9800236Abstract: A pulse width modulation (PWM) system comprises an analog component and a digital component. The analog component introduces an offset (i.e., a time delay) to analog signals being received at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises an analog delay line comprising a plurality of analog delay components configured to introduce the time delay to the analog signals based on a model of a transmission line.Type: GrantFiled: November 10, 2015Date of Patent: October 24, 2017Assignee: Infineon Technologies AGInventors: Yannis Papananos, David Seebacher, Nikolaos Alexiou, Franz Dielacher
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Publication number: 20170134194Abstract: A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.Type: ApplicationFiled: November 10, 2015Publication date: May 11, 2017Inventors: Yannis Papananos, David Seebacher, Nikolaos Alexiou, Franz Dielacher, Konstantinos Galanopoulos, Peter Singerl, Marc Tiebout
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Publication number: 20170134015Abstract: A pulse width modulation (PWM) system comprises an analog component and a digital component. The analog component introduces an offset (i.e., a time delay) to analog signals being received at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises an analog delay line comprising a plurality of analog delay components configured to introduce the time delay to the analog signals based on a model of a transmission line.Type: ApplicationFiled: November 10, 2015Publication date: May 11, 2017Inventors: Yannis Papananos, David Seebacher, Nikolaos Alexiou, Franz Dielacher
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Patent number: 8505193Abstract: Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers and methods of manufacturing thereof. The manufacturing process comprises forming of a first winding in a first metal layer; forming an insulating layer over at least the first metal layer; forming of a second winding in a second metal layer such that the second winding path has both a vertical and a horizontal displacement to the first conductive path, preferably with an overlap that is less than a full overlap; and forming shunts to ensure continuity of each of the first and second windings.Type: GrantFiled: May 16, 2012Date of Patent: August 13, 2013Assignee: Theta Microelectronics, Inc.Inventor: Yannis Papananos
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Publication number: 20120223176Abstract: Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers and methods of manufacturing thereof. A displacement between the conductive paths of the top inductor and the bottom inductor is shown that provides for superior performance over prior art solutions.Type: ApplicationFiled: May 16, 2012Publication date: September 6, 2012Applicant: THETA MICROELECTRONICS, INC.Inventor: Yannis Papananos
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Patent number: 8183970Abstract: Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers and methods of manufacturing thereof. A displacement between the conductive paths of the top inductor and the bottom inductor is shown that provides for superior performance over prior art solutions.Type: GrantFiled: October 4, 2010Date of Patent: May 22, 2012Assignee: Theta Microelectronics, Inc.Inventor: Yannis Papananos
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Publication number: 20110018672Abstract: Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers. A displacement between the conductive paths of the top inductor and the bottom inductor is shown that provides for superior performance over prior art solutions.Type: ApplicationFiled: October 4, 2010Publication date: January 27, 2011Applicant: THETA MICROELECTRONICS, INC.Inventor: Yannis Papananos
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Patent number: 7808356Abstract: Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers. A displacement between the conductive paths of the top inductor and the bottom inductor is shown that provides for superior performance over prior art solutions.Type: GrantFiled: June 22, 2007Date of Patent: October 5, 2010Assignee: Theta Microelectronics, Inc.Inventor: Yannis Papananos
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Patent number: 7554397Abstract: A predistortion method for CMOS Low-Noise-Amplifiers (LNAs) to be used in Broadband Wireless applications is presented. The method is based on the nulling of the third order Intermodulation distortion (IMD3) of the main amplifier by a highly nonlinear predistortion branch. Maximum third order product cancellation is ensured by a transformer feedback method. The technique improves linearity in a wide range of input power without significant gain and Noise Figure (NF) degradation. Simulation results on a 1-V LNA indicate a 10.3 dB improvement in the Input Third-Order Intercept Point (IIP3) with a reduction of only 1 dB and 0.44 dB in amplifier gain and NF respectively.Type: GrantFiled: May 10, 2007Date of Patent: June 30, 2009Assignee: Theta Microelectronics, Inc.Inventors: Georgios Vitzilaios, Yannis Papananos
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Patent number: 7489192Abstract: A low-noise amplifier, that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance, is shown. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without Noise Figure degradation.Type: GrantFiled: May 14, 2007Date of Patent: February 10, 2009Assignee: Theta Microelectronics, Inc.Inventors: Georgios Vitzilaios, Yannis Papananos
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Publication number: 20080100374Abstract: Programmable filters are used for the purpose of changing the filter cutoff frequency as may be necessary for the operation of a wireless transmitter or receiver. Frequencies may be changed by selecting a desirable value of a capacitor and/or a resistor. The programmable filter controls the frequency according to the disclosed method. Furthermore, in order to reduce the area consumed by the programmable filter a three-dimensional layout is used. In accordance with the disclosed invention it is possible to program the input of the programmable filter to have a higher or lower input resistance as may be required while maintaining the desired programmed cutoff frequency by switching the respective capacitors in a capacitor bank, thereby combining the elements needed for frequency programmability and input impedance level selection.Type: ApplicationFiled: October 30, 2006Publication date: May 1, 2008Inventors: Yannis Papananos, Yannis Tsividis
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Publication number: 20070290745Abstract: A low-noise amplifier, that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance, is shown. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without Noise Figure degradation.Type: ApplicationFiled: May 14, 2007Publication date: December 20, 2007Inventors: Georgios Vitzilaios, Yannis Papananos
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Publication number: 20070285162Abstract: A predistortion method for CMOS Low-Noise-Amplifiers (LNAs) to be used in Broadband Wireless applications is presented. The method is based on the nulling of the third order Intermodulation distortion (IMD3) of the main amplifier by a highly nonlinear predistortion branch. Maximum third order product cancellation is ensured by a transformer feedback method. The technique improves linearity in a wide range of input power without significant gain and Noise Figure. (NF) degradation. Simulation results on a 1-V LNA indicate a 10.3 dB improvement in the Input Third-Order Intercept Point (IIP3) with a reduction of only 1 dB and 0.44dB in amplifier gain and NF respectively.Type: ApplicationFiled: May 10, 2007Publication date: December 13, 2007Inventors: Georgios Vitzilaios, Yannis Papananos
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Publication number: 20070247269Abstract: Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers. A displacement between the conductive paths of the top inductor and the bottom inductor is shown that provides for superior performance over prior art solutions.Type: ApplicationFiled: June 22, 2007Publication date: October 25, 2007Inventor: Yannis Papananos
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Patent number: 7253712Abstract: Integrated high frequency balanced-to-unbalanced transformers suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the primary and secondary inductors for the minimization of capacitive effects between layers while using a minimal number of metal layers. Two solutions are provided, one having embodiments with a symmetrical primary inductor in a 4-metal layer implementation and one having embodiments with a non-symmetrical primary inductor in a 3-metal layer implementation.Type: GrantFiled: August 22, 2005Date of Patent: August 7, 2007Assignee: Theta Microelectronics, Inc.Inventor: Yannis Papananos