Abstract: The dual gate array substrate of the present disclosure includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs and a plurality of common electrode lines, each common electrode line is arranged between two pixel units in a same pixel pair and is connected to common electrodes of the two pixel units through two first vias; a layer where the common electrode line is located and a layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other; the two first vias are on both sides of the data line.

Abstract: An array substrate and a touch display device are provided. In the array substrate, a first control unit and a second control unit are arranged opposite to each other in a first direction. A plurality of touch sensor blocks includes a first group of electrode blocks and a second group of electrode blocks arranged in the first direction, and a plurality of touch signal lines includes a first group of touch signal lines and a second group of touch signal lines arranged in the first direction. The touch signal lines in the first group of touch signal lines are coupled to the touch sensor blocks in the first group of electrode blocks respectively; and the touch signal lines in the second group of touch signal lines are coupled to the touch sensor blocks in the second group of electrode blocks respectively.

Abstract: The present disclosure provides a liquid crystal display panel and a liquid crystal display device. The liquid crystal display panel includes a plurality of sub-pixels defined by a light shielding matrix, and an array substrate and an opposing substrate arranged to be spaced apart from each other. The opposing substrate includes a first substrate and a plurality of spacers, wherein the spacers are on a side of the first substrate close to the array substrate and being within a light shielding area of the light shielding matrix. The array substrate includes a second substrate and a plurality of protrusion structures, wherein the protrusion structures are on a side of the second substrate close to the opposing substrate, and being within the light shielding area of the light shielding matrix.

Abstract: The embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a display area and a bezel area located at the periphery of the display area; a plurality of gate lines extending from the display area to the bezel area; a plurality of shift registers located in the bezel area on at least one side of the display panel and connected to the plurality of gate lines in one-to-one correspondence. The plurality of shift registers on the bezel area on any one side of the display panel are divided into at least two groups sequentially arranged along a first direction away from the display area; the shift registers in each group are sequentially arranged along a second direction; and an angle between the second direction and the first direction is greater than 0°.

Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit includes M shift registers and N clock signal lines; every N adjacent shift registers among the M shift registers are respectively connected to the N clock signal lines, where N is an even number greater than or equal to 4, and M is an integer greater than or equal to N; a signal output terminal (OUTPUT) of an ith shift register is connected to a signal input terminal (INPUT) of a (i+p)th shift register, where (N?4)/2?p?N/2, and i is taken from 1 to (M?p); and a pull-up reset signal terminal of a jth shift register is connected to a signal output terminal (OUTPUT) of a (j+q)th shift register, where 1<q?p<N/2, and j is taken from 1 to (M?q).

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: The present disclosure provides a chip-on-film, a display substrate, a display device and a driving method. The display substrate includes a plurality of scanning lines and a plurality of cascaded shift register units coupled to the scanning lines. The display substrate further includes an output control signal line electrically coupled to each shift register unit for providing an enable signal for the shift register unit. The output control signal lines include at least two output control signal lines for providing different enable signals, and two adjacent cascaded shift register units are coupled to different output control signal lines.

Abstract: A display apparatus includes: a display panel; a backlight assembly including a light source; and an optical film group including: a functional material layer; wherein: the light source is configured to emit a white light; and the functional material layer is configured to absorb light in at least one of a range of 480 nm-520 nm or a range of 575 nm-600 nm to thereby reshape the white light to have blue, red, and green peaks; and the display apparatus further includes a polarizer (POL) including one or more polarizer sub-layers, wherein the functional material layer and one of the one or more polarizer sub-layers are configured as one same layer.

Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1?k?K?N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n?i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1<n<N, (K?2)/2?i?K/2, and K/2<j?K?2. K=12, the input signal terminal of the n-th stage is connected to an output signal terminal of a (n?6)-th stage, and the reset signal terminals of the n-th stage and the (n+1)-th stage are connected to an output signal terminal of a (n+8)-th stage or a (n+10) stage.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: An array substrate and a touch display device are provided. In the array substrate, a first control unit and a second control unit are arranged opposite to each other in a first direction. A plurality of touch sensor blocks includes a first group of electrode blocks and a second group of electrode blocks arranged in the first direction, and a plurality of touch signal lines includes a first group of touch signal lines and a second group of touch signal lines arranged in the first direction. The touch signal lines in the first group of touch signal lines are coupled to the touch sensor blocks in the first group of electrode blocks respectively; and the touch signal lines in the second group of touch signal lines are coupled to the touch sensor blocks in the second group of electrode blocks respectively.

Abstract: A display module and a display apparatus, relate to the technical filed of display. At least one chip group and a group of first PLG wirings corresponding to each of the chip groups are disposed in a first bonding area, each of the chip groups includes at least two groups of chip units, each group of the chip units includes at least one gate drive chip, each group of the first PLG wirings includes a first wiring and at least one second wiring; power pins of any two adjacent gate drive chips are connected by the first wiring, each of the second wirings surrounds and passes through each of the gate drive chips, the first wirings connected with the power pin of the last gate drive chip in the previous group of the chip units and any of the second wirings, are parallelly connected with the power pin of the first gate drive chip in the next group of the chip units, to reduce the luminance difference of pixels driven by the gate drive chips in each group of the chip units.

Abstract: A display driving method, a display driving device and a display device are provided. The display driving method includes: when displaying an odd-numbered frame, providing first parity row data of the odd-numbered frame to a display array, to enable a third parity row of the display array to be displayed based on real data of the first parity row data and enable a fourth parity row of the display array to be displayed based on interpolation data of the first parity row data; and when displaying an even-numbered frame, providing second parity row data of the even-numbered frame to the display array, to enable the fourth parity row of the display array to be displayed based on real data of the second parity row data and enable the third parity row of the display array to be displayed based on interpolation data of the second parity row data.

Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n?i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n?i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N?j+1)-th to N-th stages of first shift registers and reset signal terminals of (N?j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.

Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1?k?K?N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n?i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1<n<N, (K?2)/2?i?K/2, and K/2<j?K?2.

Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a first substrate; at least one underlaying structure, arranged on the first substrate and in a non-display region of at least one side of a display region of the display panel; and at least one supporting structure, arranged on one side, facing away from the first substrate, of the at least one underlaying structure, where an orthographic projection of the supporting structure on the first substrate is within a range of an orthographic projection of the underlaying structure on the first substrate.

Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a first substrate; at least one underlaying structure, arranged on the first substrate and in a non-display region of at least one side of a display region of the display panel; and at least one supporting structure, arranged on one side, facing away from the first substrate, of the at least one underlaying structure, where an orthographic projection of the supporting structure on the first substrate is within a range of an orthographic projection of the underlaying structure on the first substrate.

Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n?i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n?i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N?j+1)-th to N-th stages of first shift registers and reset signal terminals of (N?j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.

Abstract: An array substrate and a display panel are described. The array substrate may include a first base; a plurality of pixel units arrayed on the first base in a row direction and a column direction; each of the pixel units comprising at least two sub-pixels arranged in the row direction; a plurality of first scanning lines sequentially arranged on the first base in the column direction, at least one first scanning line being arranged at a side of each row of pixel units in the column direction, the first scanning lines being connected with the sub-pixels; and a plurality of second scanning lines sequentially arranged on the first base in the row direction, at least one second scanning line being arranged at a side of each column of pixel units in the row direction.

Abstract: The disclosure provides a display device and a holographic display apparatus. The display device includes a display panel including a first linear polarizer located on a light-emitting side, so that the display panel emits linearly polarized image light; and a phase modulation panel disposed on the light-emitting side of the display panel and configured to perform phase modulation on the linearly polarized image light. The holographic display apparatus includes the display device.