Abstract: A display panel including: a first pixel group located in a first display region and including first light-emitting sub-pixels; a plurality of second sub-pixels located in a second display region; a third pixel group located in a transition display region and including a plurality of third light-emitting sub-pixels; a plurality of first pixel circuits located in the transition display region, the first pixel circuits are electrically connected to the first light-emitting sub-pixels for driving the first light-emitting sub-pixels to display; a plurality of second pixel circuits located in the second display region, the second pixel circuits are electrically connected to the second sub-pixels for driving the second sub-pixels to display; and a plurality of third pixel circuits located in the transition display region, the third pixel circuits are electrically connected to the third light-emitting sub-pixels for driving the third light-emitting sub-pixels to display.

Abstract: A transmitting apparatus includes a signal generation circuit and an adjustment circuit. The signal generation circuit is configured to send, to a receiving apparatus, a serial data signal that carries a training sequence and valid data, where the training sequence is used to train a skew or an equalization of the serial data signal, and the valid data is used to detect an amplitude of the serial data signal. The adjustment circuit is configured to receive indication information from the receiving apparatus, and adjust a transmission parameter of the serial data signal based on the indication information, where the transmission parameter includes at least one of the skew, the equalization, or the amplitude.

Abstract: A transmission system for converting a signal of a 9-channel encoder into a 1000 Mbps PHY signal, includes a PHY chip circuits U1 and U2, digital photocouplers U3˜U11, 485 transceivers U12˜U20, RJ45 isolation transformer-integrated jacks J1 and J2, a field programmable gate array (FPGA) chip circuit, an electronic propulsion control system (EPCS) configuration chip circuit, a Jtag interface and SM-6P-PCB jackets J3˜J11, wherein two-channel MII digital signal output and input ends of the FPGA chip circuit are respectively connected with MII digital signal input and output ends of the PHY chip circuits U1 and U2; differential data signal output and input ends of the PHY chip circuits U1 and U2 are respectively connected to the RJ45 isolation transformer-integrated jacks J1 and J2, and a master station and a slave station are arranged at the same time.

Abstract: A transmission system for converting a signal of a 9-channel encoder into a 1000 Mbps PHY signal, includes a PHY chip circuits U1 and U2, digital photocouplers U3˜U11, 485 transceivers U12˜U20, RJ45 isolation transformer-integrated jacks J1 and J2, a field programmable gate array (FPCiA) chip circuit, an electronic propulsion control system (EPCS) configuration chip circuit, a Jtag interface and SM-6P-PCB jackets J3˜J11, wherein two-channel MII digital signal output and input ends of the FPGA chip circuit are respectively connected with MII digital signal input and output ends of the PHY chip circuits U1 and U2; differential data signal output and input ends of the PHY chip circuits U1 and U2 are respectively connected to the RJ45 isolation transformer-integrated jacks J1 and J2, and a master station and a slave station are arranged at the same time.