Abstract: A semiconductor device includes a substrate, an epitaxial layer, a well region, a current spreading layer, a source region, a base region and a gate layer. The epitaxial layer is on the substrate. The well region is in the epitaxial layer. The current spreading layer is in the epitaxial layer and below the well region. The current spreading layer includes a plurality of the first doped regions and a plurality of the second doped regions, the first doped regions includes a plurality of dopants of the first semiconductor-type, the second doped regions includes a plurality of dopants of the second semiconductor-type, and the second semiconductor-type is different from the first semiconductor-type. The source region is in the well region. The base region is in the well region and adjacent to the source region. The gate layer is over the epitaxial layer.

Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

Abstract: A simulated configuration evaluation apparatus is provided. The apparatus generates a virtual three-dimensional object placed in a first simulated pose based on a virtual three-dimensional object model in a virtual space, the virtual three-dimensional object includes transmitters, the transmitters are set on the virtual three-dimensional object in a first configuration, and the transmitters are configured to transmit a plurality of first signals. The apparatus receives second signals from the transmitters based on a viewpoint in the virtual space. The apparatus calculates a first estimated pose of the virtual three-dimensional object in the virtual space based on the second signals. The apparatus compares the first estimated pose and the first simulated pose to generate a first evaluating score corresponding to the first configuration.

Abstract: A circuit board module includes a circuit board and a plurality of capacitors. The circuit board has a plurality of standing feet for erecting on a main board, and the capacitors are symmetrically fixed on a first surface and a second surface opposite to the first surface of the circuit board. An opening is formed on the circuit board of the circuit board module and the opening is located between the capacitors. In addition, an electronic device adopting the circuit board module design is also disclosed herein.

Abstract: Some embodiments of the present disclosure provide a method of forming a semiconductor device including forming a dielectric layer stack on an epitaxial layer. The dielectric layer stack includes at least one first layer and at least one second layer, the at least one first layer is made of a first material, the at least second layer is made of a second material different from the first material. The dielectric layer stack is patterned to form a staircase-shaped dielectric layer stack. An ion implantation process is performed to the epitaxial layer by using the staircase-shaped dielectric layer stack.

Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

Abstract: A semiconductor device includes a substrate, a drift region, a well region, a first shield region, a junction gate field-effect transistor (JFET) region, a source region and a gate structure. The first shield region is located in the drift region, in which a bottom surface of the first shield region is lower than a bottom surface of the well region and a carrier concentration of the first shield region is greater than a carrier concentration of the well region. The JFET region is located in the drift region, in which a bottom surface of the JFET region is lower than a bottom surface of the first shield region. A first portion of the first shield region is located between the well region and the JFET region. The source region is adjacent to the well region. The gate structure is located on the drift region.

Abstract: A semiconductor device includes a substrate, a drift region, a channel region, a source region, a gate electrode layer and a gate pad. The drift region is located in the substrate. The gate electrode layer is located above the drift region and is adjacent to the channel region and the source region, in which the gate electrode layer includes a cell area, a connection area and a gate pad area. The cell area at least covers the channel region in the substrate. The connection area is adjacent to the cell area, in which the connection area has at least one opening that penetrates the connection area. The gate pad contacts the gate pad area of the gate electrode layer, in which the gate pad and the at least one opening of the connection area of the gate electrode layer is laterally separated.

Abstract: A power semiconductor device includes a substrate, an epitaxy layer, a source electrode, and a first metal layer. The substrate includes an active region, a buffer region, and a termination region. The buffer region surrounds the active region, and the termination region surrounds the active region. The epitaxy layer is located on the substrate. The epitaxy layer is located in the active region, the buffer region, and the termination region. The epitaxy layer has a first conductive type. The source electrode is located in the active region. The first metal layer is located in the buffer region. The first metal layer is connected to the source electrode.

Abstract: The present disclosure provides object tracking method and system. The object tracking method is applicable to the object tracking system configured to track a target object. The object tracking method includes: by a first tracking equipment, obtaining first spatial relationship information between an electronic device and an anchor object; by a second tracking equipment, obtaining second spatial relationship information between the anchor object and the target object; and by an information processor, calculating spatial information of the target object in relation to the electronic device according to the first spatial relationship information and the second spatial relationship information.

Abstract: A semiconductor device includes an epitaxial layer, a gate structure, a well, and a source electrode. The epitaxial layer has a first conductive type. The gate structure is disposed in the epitaxial layer and has a curved surface protruding into the epitaxial layer. A breadth depth ratio of the gate structure is less than or equal to 1. The well is disposed in the epitaxial layer. The well has a second conductive type different from the first conductive type. The well extends into the epitaxial layer along the curved surface of the gate structure. The well is in contact with the curved surface. The source electrode is disposed above the epitaxial layer and is electrically connected to the well.

Abstract: A semiconductor device includes an epitaxial layer, a gate structure, a well, and a source electrode. The epitaxial layer has a first conductive type. The gate structure and the well are disposed in the epitaxial layer. The well has a second conductive type different from the first conductive type. The well extends from a sidewall of the gate structure to a bottom surface of the gate structure. The source electrode is disposed above the epitaxial layer and is electrically connected to the well.

Abstract: A semiconductor device includes a substrate, a source trench structure, a gate trench structure and a drain electrode. The source trench structure is in the substrate. The gate trench structure is in the substrate, and a bottom of the gate trench structure is higher than a bottom of the source trench structure. The gate trench structure surrounds the source trench structure and defines a device unit, and a first projection area of the source trench structure along a fixed direction is less than 20% of a second projection area of the device unit along the fixed direction. The drain electrode is below the substrate.

Abstract: The present disclosure provides object tracking method and system. The object tracking method is applicable to the object tracking system configured to track a target object. The object tracking method includes: by a first tracking equipment, obtaining first spatial relationship information between an electronic device and an anchor object; by a second tracking equipment, obtaining second spatial relationship information between the anchor object and the target object; and by an information processor, calculating spatial information of the target object in relation to the electronic device according to the first spatial relationship information and the second spatial relationship information.

Abstract: A manufacturing method of a semiconductor device includes forming an epitaxial layer over a substrate, forming a well region and a source region in the epitaxial layer, forming a first trench in the epitaxial layer, in which the first trench has a round corner protruding to the well region, forming a second trench in the epitaxial layer, in which the bottom of the second trench is higher than the bottom of the first trench and the width of the second trench is greater than the width of the first trench, and forming a gate structure in the first trench and the second trench.

Abstract: A method includes forming a trench in a substrate, the trench extending downwards from a top surface of the substrate, in which the trench has a sidewall and a bottom surface, and an angle between the sidewall and the bottom surface is greater than or equal to 90 degrees, forming a well region at the top surface of the substrate, the sidewall and the bottom surface of the trench, forming a source region and a body contact region at the bottom surface of the trench, and the body contact region being adjacent to the source region, forming a gate structure along the top surface of the substrate, the sidewall and the bottom surface of the trench, and forming a source contact in the trench to penetrate the gate structure and electrically connect to the source region and the body contact region.

Abstract: A semiconductor structure includes a substrate, a gate structure, a first oxide layer, and a second oxide layer. The substrate has a trench. An inclined surface and a bottom surface of the trench have an obtuse angle therebetween. The gate structure is located in the trench. A width of a bottom surface of the gate structure is less than a width of a top surface of the gate structure. A cross-sectional profile of the gate structure is inverted trapezoid. The first oxide layer is located between the gate structure and the substrate. The second oxide layer is located on the top surface of the gate structure.

Abstract: A manufacturing method of a semiconductor device includes providing a substrate, forming a first trench in the substrate, in which a top of the first trench is greater than a bottom of the first trench, forming a well region and a source region at a side of the first trench, in which the source region is on the well region, forming a hard mask stack lining a surface of the substrate, forming a second trench in the hard mask stack, in which the bottom of the second trench is over the corner of the first trench, performing an implantation process to form a shielding doped region at a region of the substrate nearing the corner of the first trench, removing the hard mask stack, forming a gate dielectric layer lining the surface of the substrate, and forming a gate in the first trench.

Abstract: A circuit board module includes a circuit board and a plurality of capacitors. The circuit board has a plurality of standing feet for erecting on a main board, and the capacitors are symmetrically fixed on a first surface and a second surface opposite to the first surface of the circuit board. An opening is formed on the circuit board of the circuit board module and the opening is located between the capacitors. In addition, an electronic device adopting the circuit board module design is also disclosed herein.

Abstract: A simulated configuration evaluation apparatus is provided. The apparatus generates a virtual three-dimensional object placed in a first simulated pose based on a virtual three-dimensional object model in a virtual space, the virtual three-dimensional object includes transmitters, the transmitters are set on the virtual three-dimensional object in a first configuration, and the transmitters are configured to transmit a plurality of first signals. The apparatus receives second signals from the transmitters based on a viewpoint in the virtual space. The apparatus calculates a first estimated pose of the virtual three-dimensional object in the virtual space based on the second signals. The apparatus compares the first estimated pose and the first simulated pose to generate a first evaluating score corresponding to the first configuration.