Abstract: A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor provides two homogeneous cores. One is used as a trusted core and the other is used as a master core. The trusted core has an access right to an isolated storage space of a system memory. The master core is a normal core that is prohibited from accessing the isolated storage space. The trusted core has a first cryptographic module. In response to a reset of the trusted core, the first cryptographic module operates for firmware verification. This is how the trusted core turns on the processor using trusted firmware.

Abstract: A coralline hydroxyapatite having a pore size of 30 ?m to 1300 ?m, a porosity of 50% to 70%, and a conversion rate of 50% or more, and a preparation method are disclosed. The preparation method comprises: soaking pretreated corallite in a cutting protective agent, and then cutting to obtain cut corallite, and screening for cut corallite that meets a cutting size requirement to obtain an acceptable product of cut corallite; fully soaking the acceptable product of cut corallite in a phosphate solution, and performing a hydrothermal exchange reaction to obtain the coralline hydroxyapatite; wherein the cutting protective agent is a solution containing a polyol. The preparation method can significantly improve the cutting efficiency, broaden the cutting specifications and sizes, and significantly improve the yield of acceptable product, especially the yield of acceptable small-size products, which further broadens the application range of artificial bones.

Abstract: A computing system with trusted computing is shown. The processor includes a normal core, and a trusted core for trusted computing. The system memory provides a normal memory, and an isolated memory for trusted computing. The chipset for the communication among the processor, the system memory, and peripherals includes a monitor and records memory protection configuration information. According to the memory protection configuration information, the monitor permits security peripherals to access the isolated memory, and prohibits normal peripherals from accessing the isolated memory.

Abstract: An oxidant for humic acid modification and a method for preparing humic acid rich in carboxyl groups are provided. The oxidant used for humic acid modification includes cobalt-nickel catalyst loaded on biochars and hydrogen peroxide solutions. When preparing humic acid rich in carboxyl groups, first dissolving the humic acid in a 2 wt % sodium hydroxide solution to prepare a sodium humate solution; then, under stirring conditions, adding the oxidant used for humic acid modification to the sodium humate solution and react at 45-55° C. for 90-150 minutes; then freeze-drying to obtain the final product. The present disclosure selectively breaks and destroys the aromatic carbon structure of humic acid by using cobalt-nickel catalyst loaded on biochar in combination with hydrogen peroxide solution, and avoids the release of carbon dioxide generated by excessive oxidation of humic acid carbon structure, thereby directionally increasing the carboxyl content of humic acid.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has first register storing a Hash value pointer, and a second register, storing a private key pointer. In response to a first elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory by referring to the first register to get a Hash value of the data to be signed, reads a private key by referring to the second register, performs a signature procedure using the elliptic curve cryptographic algorithm on the Hash value based on the private key to generate a digital signature, and programs the digital signature into a second storage space within the system memory.

Abstract: The present disclosure belongs to the technical field of efficient utilization of fertilizers, and specifically relates to a pH-buffering synergistic carrier for reducing ammonia volatilization in urea, and a preparation method and use thereof. In the present disclosure, a hydroxyl-containing organic acid and alkali are used as raw materials to obtain a pH buffer. A pH buffer performance protectant prepared from chelating precipitant as a main raw material is combined with the pH buffer to prepare the pH-buffering synergistic carrier. The pH buffer protection agent prevents the pH buffer from reacting with metal ions in the soil. The pH-buffering synergistic carrier is combined with urea, and an R—CO—NH—CO—NH2 structure formed by R—COOH in the carrier and an amino group of the urea can effectively enhance a stability of the pH value in a urea fertilizer micro-domain, thus ensuring the supply of a nitrogen fertilizer while reducing ammonia volatilization losses.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a public key pointer pointing to a public key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a plaintext input from a first storage space within a system memory, performing an encryption procedure using the elliptic curve cryptographic algorithm on the plaintext input based on the public key obtained by referring to the first register to encrypt the plaintext input and to generate a ciphertext output, and programming the ciphertext output into a second storage space within the system memory.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. Three elliptic curve cryptographic instructions are proposed in the instruction set architecture for key exchange between an initiator and a responder. The initiator device executes the first elliptic curve cryptographic instruction to generate a key pair (rA, RA). In addition to considering the first temporary public key RA, the responder device further takes the second temporary public key RB into consideration when executing the second elliptic curve cryptographic instruction to generate the responder-generated shared key KB. Based on the temporary private key rA, and the temporary public keys RA and RB, the initiator device executes the third elliptic curve cryptographic instruction to generate the initiator-generated shared key KA.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor has a trusted core, a normal core, and a shared cache. The trusted core has an access right to an isolated storage space of a system memory. The normal core is homogeneous with the trusted core, and is prohibited from accessing the isolated storage space. In response to a cache flush instruction issued by the normal core, the trusted core initiates and executes a second cache write-back instruction that is different from the first cache write-back instruction. According to the second cache write-back instruction, isolated data associated with the isolated storage space and cached in the shared cache is written back to the isolated storage space before being flushed.

Abstract: A processor with a Hash cryptographic algorithm and a data processing method are shown. In response to one single Hash cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory to obtain an input message of a limited length, and processes the input message in accordance with the Hash cryptographic algorithm to generate a final Hash value of a specific length.

Abstract: The present invention relates to a method for preparing a humic acid-containing synergistic carrier for accelerating urea conversion. The preparation method includes steps of, for example, preparing an extractant for humic acid, preparing a humic acid extract and preparing a humic acid-containing synergistic carrier. Combination of the humic acid-containing synergistic carrier with urea can accelerate urea conversion, and the residual urea rate will be reduced by 22.7%-29.1% than a commercially available urea. The present invention provides a new idea for improving the utilization rate of nitrogen fertilizer in soil with low urease activity. Compared with a commercially available urea, the urea containing the humic acid-containing synergistic carrier of the present invention can increase the rice yield and the utilization rate of nitrogen fertilizer by 9.7% and 8.3%, respectively.

Abstract: The present invention relates to an organic nutrient-based dissolution accelerator for potassium sulfate and a preparation method therefor and the use thereof. The organic nutrient-based dissolution accelerator for potassium sulfate of the present invention consists of an organic acid mixture solution, tyrosine, leucine, threonine, alcohol amine, and the like. The organic nutrient-based dissolution accelerator for potassium sulfate of the present invention can not only substantially improve the dissolution speed of potassium sulfate by 6-120 times, but also provides organic nutrition for crops to achieve a synergy with inorganic nutrition to further improve the nutritional efficiency of potassium and sulfur elements.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. Three elliptic curve cryptographic instructions are proposed in the instruction set architecture for key exchange between an initiator and a responder. The initiator device executes the first elliptic curve cryptographic instruction to generate a key pair (rA, RA). In addition to considering the first temporary public key RA, the responder device further takes the second temporary public key RB into consideration when executing the second elliptic curve cryptographic instruction to generate the responder-generated shared key KB. Based on the temporary private key rA, and the temporary public keys RA and RB, the initiator device executes the third elliptic curve cryptographic instruction to generate the initiator-generated shared key KA.

Abstract: A processor with a block cipher algorithm and a data encryption and decryption method operated by the processor are shown. The processor uses a register to store an input key pointer pointing to an input key. In response to one single block cipher instruction of an instruction set architecture (ISA), the processor obtains input data from a first system memory area, performs the block cipher algorithm on the input data based on the input key indicated by the input key pointer stored in the register to encrypt or decrypt the input data to generate output data, and stores the output data in a second system memory area, or an internal storage area within the processor.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a private key pointer pointing to a private key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a ciphertext input from a first storage space within a system memory, performing a decryption procedure using the elliptic curve cryptographic algorithm on the ciphertext input based on the private key obtained by referring to the first register to decrypt the ciphertext input and generate a plaintext output, and programming the plaintext output into a second storage space within the system memory.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register storing a Hash value pointer, a second register storing a public key pointer, a third register storing a signature pointer, and a fourth register for storage of a verified result. In response to a first elliptic curve cryptographic instruction of an instruction set architecture, the processor reads the Hash value of the data by referring to the first register, obtains the public key by referring to the second register, obtains the digital signature to be verified by referring to the third register, performs a signature verification procedure using the elliptic curve cryptographic algorithm on the Hash value based on the public key and the digital signature to be verified to generate the verified result, and programs the verified result into the fourth register.

Abstract: A processor with protection of an isolated memory and protection method for the isolated memory accessible only by a trusted core are shown. A processor has a trusted core with a right to access an isolated memory planned on a system memory, a normal core prohibited from accessing the isolated memory, and a last-level cache shared by the trusted core and the normal core. The in-core cache structure of the normal core and the last-level cache are included in a hierarchical cache system. In response to a memory access request issued by the normal core, the hierarchical cache system determines whether the memory access request hits the isolated memory and, if yes, the hierarchical cache system rejects the memory access request.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor provides two homogeneous cores. One is used as a trusted core and the other is used as a master core. The trusted core has an access right to an isolated storage space of a system memory. The master core is a normal core that is prohibited from accessing the isolated storage space. The trusted core has a first cryptographic module. In response to a reset of the trusted core, the first cryptographic module operates for firmware verification. This is how the trusted core turns on the processor using trusted firmware.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor has a trusted core, a normal core, and a shared cache. The trusted core has an access right to an isolated storage space of a system memory. The normal core is homogeneous with the trusted core, and is prohibited from accessing the isolated storage space. In response to a cache flush instruction issued by the normal core, the trusted core initiates and executes a second cache write-back instruction that is different from the first cache write-back instruction. According to the second cache write-back instruction, isolated data associated with the isolated storage space and cached in the shared cache is written back to the isolated storage space before being flushed.