Abstract: A NAND ferroelectric memory cell with a three-dimensional structure and a preparation method thereof are provided, the ferroelectric memory cell comprises: an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer, and/or a gate buffer layer, and a gate arranged successively from the inside to the outside. In the memory cell of the present disclosure, the buffer layer has the following effects: 1. It can induce the crystallization of ferroelectric film to form ferroelectric phase; 2. It can reduce adverse effects caused by different crystalline characteristics of the channel layer and the ferroelectric layer, improve the quality and uniformity of the deposited film; 3. It can enhance the interface property of the channel layer, reduce leakage current, and enhance endurance of the device. Therefore, the buffer layer can improve the overall storage property and homogeneity of memory cells with a three-dimensional structure.

Abstract: A method and apparatus for on-line measurement of the wafer thinning and grinding force, related to the field of ultra-precision machining of semiconductor wafer materials. The grinding force measuring apparatus comprises a semiconductor wafer, a worktable, a bearing table, a thin film pressure sensor, and a data processing and wireless transmission module. The grinding force measuring method includes sensor calibration based on the testing device and on-line measurement of grinding force. Using the grinding force measuring device and method provided by the invention, the grinding force in the semiconductor wafer grinding process can be monitored in real time, which is of great significance for semiconductor processing and reducing grinding damage.

Abstract: The invention discloses a packaging structure and manufacturing method of a SiC MOSFET module, which is composed of SiC MOSFET chips, upper DBC substrate, lower DBC substrate, ceramic interposer, silicon oxide dielectric layer, nano silver pastes, redistribution layer, through-ceramic-hole conductive metals and power terminals. The SiC MOSFET chips are connected to the lower DBC substrate using nano silver pastes in the invention. Besides, some rectangular frames are made on the ceramic interposer, and the SiC MOSFET chips are embedded in the ceramic interposer by filling dielectric materials. The upper surfaces of the chips and the ceramic interposer are covered with a conductive metal redistribution layer, and the upper and lower surfaces of the ceramic interposer are interconnected with the upper and lower DBC substrates, respectively. The power terminals are led out from the conductive copper layers of the upper and lower DBC substrates.

Abstract: A method and apparatus for on-line measurement of the wafer thinning and grinding force, related to the field of ultra-precision machining of semiconductor wafer materials. The grinding force measuring apparatus comprises a semiconductor wafer, a worktable, a bearing table, a thin film pressure sensor, and a data processing and wireless transmission module. The grinding force measuring method includes sensor calibration based on the testing device and on-line measurement of grinding force. Using the grinding force measuring device and method provided by the invention, the grinding force in the semiconductor wafer grinding process can be monitored in real time, which is of great significance for semiconductor processing and reducing grinding damage.

Abstract: The invention discloses a packaging structure and manufacturing method of a SiC MOSFET module, which is composed of SiC MOSFET chips, upper DBC substrate, lower DBC substrate, ceramic interposer, silicon oxide dielectric layer, nano silver pastes, redistribution layer, through-ceramic-hole conductive metals and power terminals. The SiC MOSFET chips are connected to the lower DBC substrate using nano silver pastes in the invention. Besides, some rectangular frames are made on the ceramic interposer, and the SiC MOSFET chips are embedded in the ceramic interposer by filling dielectric materials. The upper surfaces of the chips and the ceramic interposer are covered with a conductive metal redistribution layer, and the upper and lower surfaces of the ceramic interposer are interconnected with the upper and lower DBC substrates, respectively. The power terminals are led out from the conductive copper layers of the upper and lower DBC substrates.