Abstract: The memory device is configured to program and erase data in a memory block according to both an SLC storage scheme and a multiple bits per memory cell (e.g., TLC) storage scheme. In operation, control circuitry receives a command to write data to the memory cells of the memory block in the TLC storage scheme and determine if already data stored in the memory block is in the SLC storage scheme or is in the TLC cell storage scheme. In response to a determination that the data contained in the memory block is in the SLC storage scheme, the control circuitry pre-programs the memory cells of the memory block and then erases the memory cells. In response to a determination that the data contained in the memory block is in the TLC storage scheme, then the control circuitry erases the memory cells without pre-programming.

Abstract: A memory device includes a memory block including a plurality of memory cells and control circuitry configured to perform a dummy read operation to transition memory cells of the memory block from a first read condition to a second read condition. To perform the dummy read operation, the control circuitry is configured to, subsequent to performing a programming operation on a selected word line and prior to performing a programming operation on a next word line, supply a first voltage pulse to bias the selected word line and previously programmed word lines in the memory block, and, while supplying the first voltage pulse, supply a second voltage pulse to bias unprogrammed word lines in the memory block including the next word line. The second voltage pulse has a lower magnitude than the first voltage pulse.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is also configured to determine an output of the analog bitscan operation. The output is one of at least three options. The circuitry is further configured to control at least one programming parameter based on the output of the analog bitscan operation.

Abstract: A method of programming a memory device is disclosed herein. The method comprises the steps of: performing a smart verify operation to acquire an initial programming voltage; performing a program operation on a selected wordline starting with the initial programming voltage; performing a bitscan operation of a highest state being verified; and based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines.

Abstract: The memory device is configured to program and erase data in a memory block according to both an SLC storage scheme and a multiple bits per memory cell (e.g., TLC) storage scheme. In operation, control circuitry receives a command to write data to the memory cells of the memory block in the TLC storage scheme and determine if already data stored in the memory block is in the SLC storage scheme or is in the TLC cell storage scheme. In response to a determination that the data contained in the memory block is in the SLC storage scheme, the control circuitry pre-programs the memory cells of the memory block and then erases the memory cells. In response to a determination that the data contained in the memory block is in the TLC storage scheme, then the control circuitry erases the memory cells without pre-programming.

Abstract: An apparatus includes control circuits configured to connect to nonvolatile memory cells. The control circuits are configured to program the plurality of nonvolatile memory cells by applying program pulses at corresponding program voltages on control gates of the nonvolatile memory cells. One or more of the program pulses ends in a fast ramp-down from the corresponding program voltage to an offset target voltage that is offset from a post-pulse voltage by a negative kick voltage.

Abstract: A memory apparatus includes memory cells configured to store a threshold voltage corresponding to data states and a control means configured to program checkpoint ones and non-checkpoint ones of the memory cells to at least one of a verify low voltage and a verify high voltage for a checkpoint state during initial program loops. The control means adjusts a bit line voltage applied to bit lines coupled to the memory cells and a subsequent quantity of subsequent program loops based on metrics associated with the memory cells exceeding the verify low voltage and the verify high voltage. The control means programs the memory cells to respective checkpoint states and non-checkpoint states by applying each of a plurality of program pulses to each of the memory cells while applying the bit line voltage to one of the bit lines associated with a given memory cell in the subsequent program loops.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. Circuitry is configured to program at least some of the plurality of memory cells in a program loop or that is configured to erase at least some of the plurality of memory cells in an erase loop. During the program loop or the erase loop, the circuitry is configured to perform a verify operation and an analog bitscan operation. In the analog bitscan operation, the circuitry counts the memory cells that pass or that fail the verify operation. The circuitry is also configured to determine an output of the analog bitscan operation, the output being one of at least three options.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is also configured to determine an output of the analog bitscan operation. The output is one of at least three options. The circuitry is further configured to control at least one programming parameter based on the output of the analog bitscan operation.

Abstract: The memory device includes a plurality of memory cells that are arranged in word lines, including a selected word line. Circuitry is configured to program at least some of the plurality of memory cells of the selected word line in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is further configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to control at least one programming parameter based on the output of the analog bitscan operation. The at least one programming parameter is an early program-verify termination parameter or a smart verify parameter.

Abstract: The memory device includes a plurality of memory cells which are arranged in a plurality of word lines. The plurality of word lines includes a selected group of word lines to be erased in an erasing operation. The memory device also includes circuitry that is configured to erase the memory cells of the selected group of word lines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase-verify operation, and an analog bitscan operation. The circuitry is configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to set at least one erase parameter based on the output of the analog bitscan operation.

Abstract: A method of programming a memory device is disclosed herein. The method comprises the steps of: performing a smart verify operation to acquire an initial programming voltage; performing a program operation on a selected wordline starting with the initial programming voltage; performing a bitscan operation of a highest state being verified; and based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines.

Abstract: A memory device includes a memory block including a plurality of memory cells and control circuitry configured to perform a dummy read operation to transition memory cells of the memory block from a first read condition to a second read condition. To perform the dummy read operation, the control circuitry is configured to, subsequent to performing a programming operation on a selected word line and prior to performing a programming operation on a next word line, supply a first voltage pulse to bias the selected word line and previously programmed word lines in the memory block, and, while supplying the first voltage pulse, supply a second voltage pulse to bias unprogrammed word lines in the memory block including the next word line. The second voltage pulse has a lower magnitude than the first voltage pulse.

Abstract: A method and system for fast transporting real-time media stream data package is based on the Real-time Transport Protocol/Real-time Transport Control Protocol of User Datagram Protocol for network nodes such as media gateway, Integrated Access Device (IAD) and multimedia terminal. The improvement of the system lies in the adding of an IP data package fast filter module, a UDP fast sending module and a policy ARP table process module based on local UDP port. The method involves: fast receiving the real-time media stream data package transmitted on the basis of RTP/RTCP protocol; fast sending the real-time media stream data package transmitted on the basis of RTP/RTCP protocol; and a policy ARP table based on UDP port and its refurbishing system.