Abstract: The drive backplane includes a pixel area and a control area outside the pixel area. The control area includes a circuit area and a bus area between the circuit area and the pixel area. The drive backplane includes a substrate and a circuit layer provided on a side of the substrate. The circuit layer includes a plurality of pixel circuits, a plurality of gate lines, a gate drive circuit, bus lines, and a plurality of gate connection lines.

Abstract: A display module includes a display substrate and a first structure layer; on a plane parallel to the display substrate the display substrate includes a display region and a bezel region wherein the bezel region is located around the display region, and is provided with first gate driving circuits of at least one type, the number of first gate driving circuits of the same type is plurality, and the first gate driving circuit includes a plurality of transistors; and in a direction perpendicular to a plane where the display substrate is located, the first structure layer is provided on a backlight side of the display substrate display substrate.

Abstract: A display substrate includes a base substrate, a first encapsulation adhesive base substrate, multiple first signal lead lines, multiple test connection traces and multiple test signal access pins. The base substrate at least includes a display area and a peripheral area located on a side of the display area. The first encapsulation adhesive base substrate is located in the peripheral area. The multiple first signal lead lines, the multiple test connection traces, and the multiple test signal access pins are located on a side of the first encapsulation adhesive base substrate away from the display area. At least one first signal lead line is electrically connected with at least one test signal access pin through at least one test connection trace.

Abstract: A display substrate and a preparation method therefor, and a display apparatus are provided. The display substrate includes a drive circuit layer (102) and a light emitting structure layer (103) arranged on a base substrate (101), the drive circuit layer (102) includes a plurality of circuit units, at least one circuit unit is provided with at least one light transmitting region, the light emitting structure layer (103) includes a plurality of light emitting units, the light emitting unit at least includes an anode, and the light transmitting region is located between adjacent anodes; and there is a first dimension between two adjacent anodes in two adjacent pixel rows, and the light transmitting region has a second dimension, wherein a ratio of the second dimension to the first dimension is greater than or equal to 0.5.

Abstract: A display substrate includes a display area and a bezel area located on a periphery of the display area. The display area includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, numbers of sub-pixels in at least part of the pixel columns are reduced in a direction close to the bezel area, and a first step-shaped display area boundary is formed on a side of the display area close to the bezel area. The bezel area at least includes a capacitance area, and the capacitance area includes a plurality of compensation capacitors forming a second step-shaped capacitance area boundary on a side away from the display area.

Abstract: A display substrate has a display region, an encapsulation region and a peripheral region. The display substrate includes a base substrate, a pixel definition layer, and a photo spacer layer. The photo spacer layer includes a plurality of peripheral photo spacers disposed in the peripheral region. A direction perpendicular to a border of the display region adjacent to the plurality of peripheral photo spacers is a first direction. In the first direction, a distance from a peripheral photo spacer of the plurality of peripheral photo spacers closest to the encapsulation region to the encapsulation region is a first distance, and a distance from the peripheral photo spacer of the plurality of peripheral photo spacers closest to the encapsulation region to the display region is a second distance. The first distance is less than or equal to the second distance.

Abstract: A display substrate comprises a base substrate, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer and at least one transparent conductive layer. The second conductive layer is electrically connected with the first conductive layer through at least one first via penetrating the first planarization layer. The transparent conductive layer includes at least one first transparent conductive line and at least one auxiliary trace. An orthographic projection of the first transparent conductive line on the base substrate is overlapped with an orthographic projection of the at least one first via on the base substrate. At least a portion of the auxiliary traces are in the same direction as an extension direction of the first transparent conductive line, and an orthographic projection of the auxiliary traces on the base substrate is adjacent to an orthographic projection of the first via on the base substrate.

Abstract: Provided is a display panel, including: a base substrate, a plurality of display sub-pixels, a plurality of power voltage lines, and a plurality of data signal lines. The display sub-pixel includes a display pixel drive circuit connected to the power voltage line and the data signal line. The display pixel drive circuit includes at least a first transistor and a second transistor. Each of the first transistor and the second transistor includes an active layer. The first transistor includes a shield. An orthographic projection of the shield on the base substrate is at least partially overlapped with an orthographic projection of a channel connection region of the active layer of the first transistor on the base substrate. An orthographic projection of the shield and the data signal line is not overlapped with an orthographic projection of the active layer of the second transistor on the base substrate.

Abstract: A display substrate comprises a display area and a bezel area, wherein a side of the display area close to the bezel area forms a first step-shaped display area boundary, the bezel area at least comprises a capacitance area, the capacitance area comprises a plurality of compensation capacitors, and the plurality of compensation capacitors form a second step-shaped capacitance area boundary on a side far away from the display area; the display area boundary comprises a plurality of first steps connected in sequence, the first steps having a first step length and a first step width, and the capacitance area boundary comprises a plurality of second steps connected in sequence.

Abstract: A display substrate and a display apparatus. The display substrate comprises a plurality of sub-pixels and a pixel definition layer, wherein a plurality of pixel openings are formed in the pixel definition layer, and each sub-pixel comprises at least one pixel opening; and the plurality of sub-pixels comprise first sub-pixels (P1), second sub-pixels (P2) and third sub-pixels (P3), at least one first sub-pixel (P1) being adjacent to both the second sub-pixel (P2) and the third sub-pixel (P3), and the minimum distance from a pixel opening (61) of the at least one first sub-pixel (P1) to a pixel opening (62) of one adjacent second sub-pixel (P2) being different from the minimum distance between the pixel opening of the at least one first sub-pixel (P1) to a pixel opening (63) of one adjacent third sub-pixel (P3).

Abstract: The present disclosure provides a display substrate, which includes a base substrate (101), a first power supply line (321a), a plurality of first signal leads (341), a plurality of test connection traces (342), at least one first connection line (381), and a plurality of test signal access pins (361). At least one first signal lead (341) is electrically connected to at least one test signal access pin (361) through at least one test connection trace (342). The first connection line (381) is located at a side of the plurality of test connection traces (342) and the plurality of test signal access pins (361) close to an edge of the peripheral area in a first direction (X). The first connection line (381) at least extends along a second direction (Y) and is electrically connected to the first power supply line (321a).

Abstract: A display substrate has a display region, an encapsulation region and a peripheral region. The display substrate includes a base substrate, a pixel definition layer, and a photo spacer layer. The photo spacer layer includes a plurality of peripheral photo spacers disposed in the peripheral region. A direction perpendicular to a border of the display region adjacent to the plurality of peripheral photo spacers is a first direction. In the first direction, a distance from a peripheral photo spacer of the plurality of peripheral photo spacers closest to the encapsulation region to the encapsulation region is a first distance, and a distance from the peripheral photo spacer of the plurality of peripheral photo spacers closest to the encapsulation region to the display region is a second distance. The first distance is less than or equal to the second distance.

Abstract: A display substrate and a display device. The display substrate includes a substrate base, a plurality of sub-pixels, and a partition structure; the partition structure includes a plurality of annular partition parts, which include a plurality of first annular partition parts, a plurality of second annular partition parts, and a plurality of third annular partition parts, the first annular partition part is around one second color sub-pixel, the second annular partition part is around one first color sub-pixel, the third annular partition part is around one third color sub-pixel, each of the plurality of first annular partition parts includes a first number of first notches, each of the plurality of second annular partition parts includes a second number of second notches, each of the plurality of third annular partition parts includes a third number of third notches, the second number is different from the third number.

Abstract: A display substrate includes a base substrate, a first encapsulation adhesive base substrate, multiple first signal lead lines, multiple test connection traces and multiple test signal access pins. The base substrate at least includes a display area and a peripheral area located on a side of the display area. The first encapsulation adhesive base substrate is located in the peripheral area. The multiple first signal lead lines, the multiple test connection traces, and the multiple test signal access pins are located on a side of the first encapsulation adhesive base substrate away from the display area. At least one first signal lead line is electrically connected with at least one test signal access pin through at least one test connection trace.

Abstract: Provided is a display panel, including: a substrate, a connection line, a first pixel drive circuit, a first insulative layer, and first light-emitting devices. The substrate includes a light-transmissive display region and a conventional display region at least partially surrounding the light-transmissive display region. The connection line and the first pixel drive circuit are disposed on the substrate. The connection line is electrically connected to the first pixel drive circuit. The first pixel drive circuit is disposed in the conventional display region. The first insulative layer is disposed on a side, distal from the substrate, of the connection line and is provided with first via holes arranged in arrays. The first light-emitting devices are disposed on a side, distal from the substrate, of the first insulative layer and arranged in arrays in the light-transmissive display region and electrically connected to the connection lines via the first via holes.

Abstract: A display motherboard comprises at least one substrate region; the substrate region comprises at least one test pad region, at least one test wire region and at least two display substrates; the test pad region comprises a plurality of pads; the test wire region comprises a plurality of signal wires, first ends of the plurality of signal wires being correspondingly connected to the plurality of pads, and second ends of the plurality of signal wires extending to the display substrates in the substrate region, so as to be connected to test circuits of the display substrates; the plurality of pads are configured to allow an external test device to provide, by means of the plurality of pads, test signals to the test circuits of the display substrates in the substrate region, so as to simultaneously perform light-on tests or aging procedures on the display substrates in the substrate region.

Abstract: A display panel includes a display substrate, where the display substrate includes a display area and a peripheral area; a plurality of light-emitting elements; an encapsulation cover plate, provided at a side of the light-emitting elements away from the display substrate; and an encapsulation structure, provided on a surface of the display substrate at a side of the peripheral area, where the encapsulation structure is located between the display substrate and is provided with a smooth curved section. A section of the display substrate covered by the encapsulation structure includes a base, an electrically conductive layer and an insulating layer stacked in sequence. The electrically conductive layer is provided with a plurality of first openings. The insulating layer fills the first opening. The insulating layer is provided with at least one second opening in a region where the first opening is located. The encapsulation structure fills the second opening.

Abstract: Provided are a display panel and a display apparatus. The display panel includes a substrate, a circuit structure layer, a light emitting structure layer and multiple transparent conductive layers. The transparent conductive layer is located between the circuit structure layer and the light emitting structure layer, and includes multiple first type conductive lines and multiple second type conductive lines. The portion of the first type conductive line extending along a first direction overlaps with an orthographic projection of the shield electrode on the substrate, and the portion of the second type conductive line extending along the first direction does not overlap with an orthographic projection of the shield electrode on the substrate.

Abstract: The present disclosure is directed to kappa opioid receptor ligands and pharmaceutical compositions thereof and their utility as neurological modulators (e.g., anti-nociceptive agents, antidepressants, anxiolytics, antipruritics). Specifically, the disclosed kappa opioid ligands are G-protein biased kappa opioid agonists containing a core and three different arms as is shown in Formula (A) below.

Abstract: The present disclosure provides a display substrate including a base substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, a plurality of first electrostatic discharge circuits, a plurality of second electrostatic discharge circuits, and a plurality of first signal lines located on the base substrate. The plurality of multiplexing circuits are sequentially arranged along edges of the display region. The plurality of multiplexing circuits are electrically connected with the plurality of multiplexing data lines and the plurality of data lines. The plurality of first electrostatic discharge circuits are electrically connected to the plurality of multiplexing data lines, and the plurality of second electrostatic discharge circuits are electrically connected to the plurality of first signal lines.