Abstract: A method for penalty-based game thread task load scheduling is described. The method includes comparing a current frames per second (FPS) value of a game thread to a target FPS value. The method also includes detecting frame headroom of the game thread when the current FPS value of the game thread is not less than the target FPS value. The method further includes penalizing a task load of the game thread in response to detecting the frame headroom. The method also includes propagating a hint to a task scheduler including the penalized task load of the game thread.

Abstract: Embodiments of the present disclosure relate to an information processing apparatus. The information processing apparatus includes: a main board, provided with a first surface, where the first surface is provided with a central processing unit electrically connected to the main board; a compression attached memory module, located on one side of the first surface, where at least one surface of the compression attached memory module is provided with a plurality of chips; and an external connecting structure, located on one side of the first surface, and configured to: electrically connect the compression attached memory module and the central processing unit, where the central processing unit is configured to: read data from and write data to each chip at least via the external connecting structure.

Abstract: A semiconductor device and a storage system are provided. The semiconductor device includes a first printed circuit board and a capacitor structure positioned on the first printed circuit board. The first printed circuit board includes a plurality of memories arranged in sequence along a first direction, and each of the memories has a first power terminal and a first ground terminal. The capacitor structure includes a plurality of capacitors, and each of the capacitors has a second power terminal corresponding to the first power terminal and a second ground terminal corresponding to the first ground terminal, wherein the first power terminal is electrically connected to the second power terminal, and the first ground terminal is electrically connected to the second ground terminal.

Abstract: Signal lines in the pin field of a printed circuit board layout are modified to reduce line impedance and improve signal integrity. The widths of signal lines are extended in the pin field to take full advantage of the available routing space between pads and adjacent signal lines. The signal line extension can be considered a subtractive approach in that the signal lines are extended to occupy the available muting space, with signal line extensions that would otherwise cause design rule violations being subtracted out. The edge of a signal line is extended to a keep-out region associated with a centerline that extends through a plurality of pads arranged in a line and located adjacent to the signal line. The edge of the signal line is also extended to keep-out regions associated with pads in the pin fields.

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a substrate, a chip stack disposed on the substrate through a plurality of first conductive structures. Each of the plurality of the first conductive structures includes a first conductive bump, and the first conductive bump includes at least one concave surface. Concave surfaces of adjacent first conductive bumps are disposed facing each other.

Abstract: A semiconductor structure includes a plurality of dies. The plurality of dies are stacked sequentially along a first direction. The first direction is a direction perpendicular to a plane of the dies. Each of the dies includes a base and n first conductive structures penetrating the base along the first direction, where n is greater than or equal to 2. In at least one group of the corresponding first conductive structures in the dies, projections of the group of the first conductive structures in two adjacent layers of the dies along the first direction are not overlapped with each other.

Abstract: A semiconductor structure includes a base, a chip stack located on the base, and first conductive structures. The chip stack includes chips stacked in sequence in a direction perpendicular to a plane of the base, a chip includes first and second sub-portions, a first surface of the first sub-portion is flush with that of the second sub-portion, a second surface of the first sub-portion protrudes from that of the second sub-portion, and the first and second surfaces are oppositely arranged. A first conductive structure includes a first conductive bump and a first through-silicon via, the first conductive bump is located between first sub-portions of two adjacent chips, the first through-silicon via penetrates through the first sub-portion in the direction perpendicular to the plane of the base and is connected to the first conductive bump, and the materials of the first conductive bump and the first through-silicon via are same.

Abstract: Disclosed are a soft solvent-free flame-retardant polyurethane synthetic leather and a preparation method therefor. The soft solvent-free flame-retardant polyurethane synthetic leather comprises an antifouling layer, a surface layer, an intermediate layer, a bonding layer and a base cloth in sequence from top to bottom, wherein the bonding layer is prepared from component A and an isocyanate; the molar ratio of —NCO in the isocyanate to —OH in the component A is 0.85-0.93; and the component A is composed of a polyhydric alcohol, an inhibition-type catalyst, a flame retardant, a filler and a viscosity modifier in parts by weight.

Abstract: A method for intelligent fault detection and location of a power distribution network is provided, which includes: constructing a network topology of the power distribution network, updating the network topology in real time to obtain an updated network topology, performing a fault identification based on the updated network topology, performing a fault locating based on the updated network topology to determine a fault node, and identifying a fault type based on a fault recorded signal of the fault node. With this method, fault locations and fault types of the power distribution network can be accurately detected in real time.

Abstract: A method for intelligent fault detection and location of a power distribution network is provided, which includes: constructing a network topology of the power distribution network, updating the network topology in real time to obtain an updated network topology, performing a fault identification based on the updated network topology, performing a fault locating based on the updated network topology to determine a fault node, and identifying a fault type based on a fault recorded signal of the fault node. With this method, fault locations and fault types of the power distribution network can be accurately detected in real time.

Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor device and a storage system. The semiconductor device includes a first printed circuit board and a capacitor structure positioned on the first printed circuit board. The first printed circuit board includes a plurality of memories arranged in sequence along a first direction, and each of the memories has a first power terminal and a first ground terminal. The capacitor structure includes a plurality of capacitors, and each of the capacitors has a second power terminal corresponding to the first power terminal and a second ground terminal corresponding to the first ground terminal, wherein the first power terminal is electrically connected to the second power terminal, and the first ground terminal is electrically connected to the second ground terminal. The semiconductor device can at least solve a problem of capacitor arrangement space, which is advantageous to optimizing power quality.

Abstract: Disclosed are a soft solvent-free flame-retardant polyurethane synthetic leather and a preparation method therefor. The soft solvent-free flame-retardant polyurethane synthetic leather comprises an antifouling layer, a surface layer, an intermediate layer, a bonding layer and a base cloth in sequence from top to bottom, wherein the bonding layer is prepared from component A and an isocyanate; the molar ratio of —NCO in the isocyanate to —OH in the component A is 0.85-0.93; and the component A is composed of a polyhydric alcohol, an inhibition-type catalyst, a flame retardant, a filler and a viscosity modifier in parts by weight. Disclosed are a soft solvent-free flame-retardant polyurethane synthetic leather and a preparation method therefor.

Abstract: A nacre-mimetic environmentally friendly composite membrane with an “interpenetrating petal” structure and a preparation method thereof. Materials for preparing the composite membrane include magadiite, CMC and a bis-silane coupling agent. The composite membrane according to the present invention has an “interpenetrating petal” stable structure with non-parallel petal-shaped lamellar structure. In addition, inorganic sheets intersperse with each other to form an interlock.

Abstract: A nacre-mimetic environmentally friendly composite membrane with an “interpenetrating petal” structure and a preparation method thereof. Materials for preparing the composite membrane include magadiite, CMC and a bis-silane coupling agent. The composite membrane according to the present invention has an “interpenetrating petal” stable structure with non-parallel petal-shaped lamellar structure. In addition, inorganic sheets intersperse with each other to form an interlock.

Abstract: Disclosed are a portable multimedia device and an operating method therefor. The portable multimedia device comprises a Flash decoder and a system function decoder.