Patents by Inventor Yanxin SU

Yanxin SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Display apparatus, display panel and manufacturing method thereof
    Patent number: 12727354
    Abstract: A display apparatus, a display panel, and a manufacturing method thereof, relate to the field of display technology. The display panel includes a substrate, a transistor layer, a wiring layer, a flat layer, and a light emitting layer. The transistor layer is disposed on a side of the substrate and includes a storage capacitor and a transistor. The material of the first type of transistor includes silicon, and material of the second type of transistor includes a metal oxide. The wiring layer is disposed on a side of the transistor layer away from the substrate and connected to the transistor layer to form a plurality of pixel circuits. The wiring layer includes a data line and a first power supply line. The flat layer covers the wiring layer. The light emitting layer is disposed on the flat layer.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: September 1, 2026
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Deng, Yue Wei, Yanxin Su, Minghui Li, Xu Yang
  • DISPLAY APPARATUS, DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
    Publication number: 20240251622
    Abstract: A display apparatus, a display panel, and a manufacturing method thereof, relate to the field of display technology. The display panel includes a substrate (SU), a transistor layer (TL), a wiring layer (SD), a flat layer (PLN), and a light emitting layer (OL). The transistor layer (TL) is disposed on a side of the substrate (SU) and includes a storage capacitor (C) and a transistor. The material of the first type of transistor includes silicon, and material of the second type of transistor includes a metal oxide. The wiring layer (SD) is disposed on a side of the transistor layer (TL) away from the substrate (SU) and connected to the transistor layer (TL) to form a plurality of pixel circuits. The wiring layer (SD) includes a data line (DAL) and a first power supply line (VDL). The flat layer (PLN) covers the wiring layer (SD).
    Type: Application
    Filed: April 25, 2022
    Publication date: July 25, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Lei DENG, Yue WEI, Yanxin SU, Minghui LI, Xu YANG