Abstract: A controller, a first voltage detector, a second voltage detector, . . . and an nth voltage detector are connected together in series in this order via a common communication line. In ID setting operation, the controller transfers a unique ID of the first voltage detector to the first voltage detector via the communication line, and transfers a unique ID of the (i+1)th voltage detector to the (i+1)th voltage detector via the first to ith voltage detectors and the communication line (where in is a natural number equal to or less than (n?1)).

Abstract: A controller, a first voltage detector, a second voltage detector, . . . and an nth voltage detector are connected together in series in this order via a common communication line. In ID setting operation, the controller transfers a unique ID of the first voltage detector to the first voltage detector via the communication line, and transfers a unique ID of the (i+1)th voltage detector to the (i+1)th voltage detector via the first to ith voltage detectors and the communication line (where in is a natural number equal to or less than (n?1)).

Abstract: Method and apparatus for receiving coded signals with the aid of CSI are provided. The method comprises: performing channel estimation to obtain a CFR estimation vector; computing a squared magnitude of the CFR estimation vector, and obtaining a normalization factor ? by averaging the squared magnitudes of CFR estimations on all N subcarriers; finding a norm-shift operand m satisfying the condition that ?0=2m is a power of 2 number closest to the normalization factor ?; performing a CSI-aided one-tap channel equalization on an output signal vector from a DFT processor by using the norm-shift operand m; performing constellation demapping; and performing channel decoding. The method further comprises obtaining a weighting factor vector by right shifting m bits of the squared magnitude of the CFR estimation vector so that the constellation demapping can use the weighted decision boundary values in case that its input signal is sensitive to both amplitude and phase.

Abstract: A system for performing LS equalization on a signal in an OFDM system comprises a receiver stage for receiving a modulated signal, a demodulation stage for demodulating the received modulated signal to produce a demodulated signal, a channel estimation stage for processing the demodulated signal to provide an output signal corresponding to a channel frequency response and an equalization stage arranged to process the output signal from the channel estimation stage to produce a channel state information signal. The equalization stage is arranged to use the channel state information signal to operate on the demodulated signal from the demodulation stage to produce an equalized demodulated output signal. There is also disclosed a method for performing LS equalization on a signal in an OFDM system.

Abstract: A method for demapping dual carrier modulated COFDM signals comprises normalizing an estimated channel state information signal to obtain a normalized channel state information signal, determining a Y-domain weighting factor from the normalized channel state information signal, determining an X-domain weighting factor from the normalized channel state information signal, performing equalization on a received data OFDM signal to obtain an equalized data signal, weighting an equalized data signal using the Y-domain weighting factor and the X-domain weighting factor to generate a weighted input signal of a demapper and performing linear demapping of the weighted input signal in the demapper. There is also disclosed an apparatus for demapping dual carrier modulated COFDM signals and a receiver comprising such an apparatus.

Abstract: A processor for performing a Fast Fourier Transform and/or an Inverse Fast Fourier Transform of a complex input signal comprises a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components of the complex input signal before passing the signal to the second stage if an Inverse Fast Fourier Transform procedure is to be performed. The second stage has first and second radix-4 butterfly elements. A third stage is arranged to switch between first and second operating modes, the second operating mode being for processing a complex conjugate symmetrical input signal. A fourth stage has a plurality of processing units, one or more of the processing units comprising a radix-2 pipelined Fast Fourier Transform processor.

Abstract: Method and apparatus for receiving coded signals with the aid of CSI are provided. The method comprises: performing channel estimation to obtain a CFR estimation vector; computing a squared magnitude of the CFR estimation vector, and obtaining a normalization factor ? by averaging the squared magnitudes of CFR estimations on all N subcarriers; finding a norm-shift operand m satisfying the condition that ?0=2m is a power of 2 number closest to the normalization factor ?; performing a CSI-aided one-tap channel equalization on an output signal vector from a DFT processor by using the norm-shift operand m; performing constellation demapping; and performing channel decoding. The method further comprises obtaining a weighting factor vector by right shifting m bits of the squared magnitude of the CFR estimation vector so that the constellation demapping can use the weighted decision boundary values in case that its input signal is sensitive to both amplitude and phase.

Abstract: A processor for performing a Fast Fourier Transform and/or an Inverse Fast Fourier Transform of a complex input signal comprises a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components of the complex input signal before passing the signal to the second stage if an Inverse Fast Fourier Transform procedure is to be performed. The second stage has first and second radix-4 butterfly elements. A third stage is arranged to switch between first and second operating modes, the second operating mode being for processing a complex conjugate symmetrical input signal. A fourth stage has a plurality of processing units, one or more of the processing units comprising a radix-2 pipelined Fast Fourier Transform processor.

Abstract: A method for demapping dual carrier modulated COFDM signals comprises normalizing an estimated channel state information signal to obtain a normalized channel state information signal, determining a Y-domain weighting factor from the normalized channel state information signal, determining an X-domain weighting factor from the normalized channel state information signal, performing equalization on a received data OFDM signal to obtain an equalized data signal, weighting an equalized data signal using the Y-domain weighting factor and the X-domain weighting factor to generate a weighted input signal of a demapper and performing linear demapping of the weighted input signal in the demapper. There is also disclosed an apparatus for demapping dual carrier modulated COFDM signals and a receiver comprising such an apparatus.

Abstract: A system for performing LS equalization on a signal in an OFDM system comprises a receiver stage for receiving a modulated signal, a demodulation stage for demodulating the received modulated signal to produce a demodulated signal, a channel estimation stage for processing the demodulated signal to provide an output signal corresponding to a channel frequency response and an equalization stage arranged to process the output signal from the channel estimation stage to produce a channel state information signal. The equalization stage is arranged to use the channel state information signal to operate on the demodulated signal from the demodulation stage to produce an equalized demodulated output signal. There is also disclosed a method for performing LS equalization on a signal in an OFDM system.