Abstract: This disclosure relates to a video compression method, apparatus, and device, and a medium. The method includes: obtaining a video frame, where the video frame includes a first dynamic group of pictures and a second dynamic group of pictures; extracting a first I frame in the first dynamic group of pictures, and extracting a second I frame in the second dynamic group of pictures; deleting duplicate data between the first I frame and the second I frame, to obtain a target I frame; and compressing the target I frame. The duplicate data between the first I frame and the second I frame is deleted, and this does not affect integrity of data of the video frame.

Abstract: An erasure code (EC)-based data processing method implemented by a storage controller includes obtaining K data chunks, dividing each of the K data chunks into two data slices, encoding the 2*K data slices based on a parity matrix including 2*M rows and 2*(K+M) columns of elements, to obtain 2*M parity slices, and separately storing the K data chunks and the M parity chunks in different storage devices.

Abstract: An erasure code (EC)-based data processing method implemented by a storage controller includes obtaining K data chunks, dividing each of the K data chunks into two data slices, encoding the 2*K data slices based on a parity matrix including 2*M rows and 2*(K+M) columns of elements, to obtain 2*M parity slices, and separately storing the K data chunks and the M parity chunks in different storage devices.

Abstract: A flash memory error correction method and apparatus is provided. The method includes determining a first data bit in a flash memory page, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold and the data obtained by reading the flash memory page using the mth read voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1)th read voltage threshold. Present disclosure effectively improves a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.

Abstract: Embodiments of the present application provide a decoding method and a decoding device. The decoding device receives a second code word, which is transmitted from an encoding device based on a first code word. The first code word is generated by the encoding device based on a first encoded data sequence. After determining that a second encoded data sequence based on the second code word is not a correct replica of the first encoded data sequence, the decoding device performs a series of code element update processes to determining the correct replica of the first encoded data sequence.

Abstract: A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). It ensures that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.

Abstract: Embodiments of the present disclosure provide a decoding method of a polar code, including: acquiring a receiving sequence and a check matrix, wherein the receiving sequence is output on a channel after an input mapping sequence is encoded; carrying out Trellis path search according to the receiving sequence and the check matrix, and calculating Trellis path likelihood information corresponding to the input mapping sequence; calculating a decision value corresponding to the input mapping sequence according to the Trellis path likelihood information; and de-mapping the calculated decision value corresponding to the input mapping sequence according to a preset mapping relation to obtain a decoding sequence. The input mapping sequence belongs to a finite field GF(q), when decoding the polar code, the Trellis path search is carried out, and the decision value is calculated and de-mapped to simultaneously reduce a maximum list value and greatly reduce an average list value.

Abstract: This application discloses a storage controller. When running, the storage controller encodes, according to a check matrix, K to-be-coded data chunks obtained from a client, to generate two check chunks. In this way, if any chunk is damaged subsequently, the damaged chunk may be recovered by using the check matrix and an undamaged chunk.

Abstract: A method (1100) for cross-polarization interference power suppression in dual-polarization radio communication systems includes: filtering (1101) a vertical polarization component (xV(n)) and a horizontal polarization component (xH(n)) of a received dual-polarization channel signal by a 2×2 channel weights matrix (507, 508); and determining (1102) the 2×2 channel weights matrix (507, 508) based on a minimum variance distortionless response criterion.

Abstract: This application discloses a storage controller. When running, the storage controller encodes, according to a check matrix, K to-be-coded data chunks obtained from a client, to generate two check chunks. In this way, if any chunk is damaged subsequently, the damaged chunk may be recovered by using the check matrix and an undamaged chunk.

Abstract: A flash memory error correction method and apparatus is provided. The method includes determining a first data bit in a flash memory page, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold and the data obtained by reading the flash memory page using the mth read voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1)th read voltage threshold. Present disclosure effectively improves a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.

Abstract: Embodiments of the present application provide a decoding method and a decoding device. The decoding device receives a second code word, which is transmitted from an encoding device based on a first code word. The first code word is generated by the encoding device based on a first encoded data sequence. After determining that a second encoded data sequence based on the second code word is not a correct replica of the first encoded data sequence, the decoding device performs a series of code element update processes to determining the correct replica of the first encoded data sequence.

Abstract: The patent application relates to a method for recovering a sparse communication signal from a receive signal, the receive signal being a channel output version of the sparse communication signal, the channel comprising channel coefficients being arranged to form a channel matrix, the method comprising determining a support set indicating a set of first indices of non-zero communication signal coefficients from the channel matrix and the receive signal, determining an estimate of the sparse communication signal upon the basis of the support set, the channel matrix and the receive signal, determining second indices of communication signal coefficients which are not indicated by the support set, and determining the sparse communication signal upon the basis of the support set, the estimate of the sparse communication signal, the second indices and the channel matrix.

Abstract: A wireless receiver being capable of determining its velocity with respect to a number of wireless transmitters is provided. The wireless receiver includes a communication interface for receiving a number of carrier signals originating from the number of wireless transmitters, and a processor being configured to determine a number of carrier phases of the carrier signals at two different time instants, to determine a number of carrier phase differences from the determined number of carrier phases for each carrier signal between the two different time instants, to determine a location matrix indicating a geometric relationship between a location of the wireless receiver and a number of locations of the number of transmitters, and to determine the velocity of the wireless receiver upon the basis of the number of carrier phase differences and the location matrix.

Abstract: A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). It ensures that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.

Abstract: A method (1100) for cross-polarization interference power suppression in dual-polarization radio communication systems includes: filtering (1101) a vertical polarization component (xV(n)) and a horizontal polarization component (xH(n)) of a received dual-polarization channel signal by a 2×2 channel weights matrix (507, 508); and determining (1102) the 2×2 channel weights matrix (507, 508) based on a minimum variance distortionless response criterion.

Abstract: The patent application relates to a method for recovering a sparse communication signal from a receive signal, the receive signal being a channel output version of the sparse communication signal, the channel comprising channel coefficients being arranged to form a channel matrix, the method comprising determining a support set indicating a set of first indices of non-zero communication signal coefficients from the channel matrix and the receive signal, determining an estimate of the sparse communication signal upon the basis of the support set, the channel matrix and the receive signal, determining second indices of communication signal coefficients which are not indicated by the support set, and determining the sparse communication signal upon the basis of the support set, the estimate of the sparse communication signal, the second indices and the channel matrix.

Abstract: Embodiments of the present disclosure provide a decoding method of a polar code, including: acquiring a receiving sequence and a check matrix, wherein the receiving sequence is output on a channel after an input mapping sequence is encoded; carrying out Trellis path search according to the receiving sequence and the check matrix, and calculating Trellis path likelihood information corresponding to the input mapping sequence; calculating a decision value corresponding to the input mapping sequence according to the Trellis path likelihood information; and de-mapping the calculated decision value corresponding to the input mapping sequence according to a preset mapping relation to obtain a decoding sequence. The input mapping sequence belongs to a finite field GF(q), when decoding the polar code, the Trellis path search is carried out, and the decision value is calculated and de-mapped to simultaneously reduce a maximum list value and greatly reduce an average list value.

Abstract: A wireless receiver being capable of determining its velocity with respect to a number of wireless transmitters is provided. The wireless receiver includes a communication interface for receiving a number of carrier signals originating from the number of wireless transmitters, and a processor being configured to determine a number of carrier phases of the carrier signals at two different time instants, to determine a number of carrier phase differences from the determined number of carrier phases for each carrier signal between the two different time instants, to determine a location matrix indicating a geometric relationship between a location of the wireless receiver and a number of locations of the number of transmitters, and to determine the velocity of the wireless receiver upon the basis of the number of carrier phase differences and the location matrix.

Abstract: A high order modulation method, a demapping method, and a corresponding device are provided. With the high order modulation method, important bits is distinguished, and the important bits are divided into important bits for distinguishing large regions and important bits for distinguishing small regions according to the difficulty of judgment areas. Therefore, the judgment accuracy rate of a demodulator is further improved.