Abstract: A circuit provides a regulated voltage supply for other circuits. The circuit includes a bias current source and a reference voltage source. The circuit includes a pass transistor and a feedback transistor. The pass transistor receives input from the feedback transistor that generates a regulated voltage at a terminal of the pass transistor. The feedback transistor receives inputs from the regulated voltage of the pass transistor and the reference voltage source. The feedback transistor provides voltage for the input of the pass transistor, thereby controlling the regulated voltage generated by the pass transistor. The regulated voltage generated by the pass transistor is provided as a regulated voltage supply to other circuits.

Abstract: A circuit provides a regulated voltage supply for other circuits. The circuit includes a bias current source and a reference voltage source. The circuit includes a pass transistor and a feedback transistor. The pass transistor receives input from the feedback transistor that generates a regulated voltage at a terminal of the pass transistor. The feedback transistor receives inputs from the regulated voltage of the pass transistor and the reference voltage source. The feedback transistor provides voltage for the input of the pass transistor, thereby controlling the regulated voltage generated by the pass transistor. The regulated voltage generated by the pass transistor is provided as a regulated voltage supply to other circuits.

Abstract: Methods and systems for storing data are disclosed. The systems are configured to perform the methods and the methods may include, for example, receiving electronic data to be stored, partitioning the data into multiple segments, and storing each segment in a memory during a separate write cycle. The methods may also include programming a compensation load so that power provided by a power supply during the storing of each segment is substantially the same.

Abstract: Methods and systems for storing data are disclosed. The systems are configured to perform the methods and the methods may include, for example, receiving electronic data to be stored, partitioning the data into multiple segments, and storing each segment in a memory during a separate write cycle. The methods may also include programming a compensation load so that power provided by a power supply during the storing of each segment is substantially the same.

Abstract: A memory system with improved power consumption and operation speed. A memory system performs a data read operation in a low power read mode to improve operation speed and reduce power consumption by biasing bit cells in the memory system at a negative voltage. The use of the negative voltage minimizes changing of voltages of the bit cells. Additionally, the memory system performs data read operation in a margin read mode to improve accuracy of the reading by biasing the bit cells at a positive voltage.

Abstract: Embodiments relate to a single multi-output high-voltage (HV) switch configured to pass multiple HV signals in semiconductor integrated circuits, such as a memory device. By utilizing a single HV switch that shares multiple components, area is reduced and fewer numbers of transistor devices are used to reduce cost. The shared components are selected such that the HV switch configuration provides functionality similar to traditional multiple HV switch configurations. Specifically, common logic shared across different branches of the single HV switch enables the single HV switch to provide multiple HV signals.

Abstract: Embodiments relate to a single multi-output high-voltage (HV) switch configured to pass multiple HV signals in semiconductor integrated circuits, such as a memory device. By utilizing a single HV switch that shares multiple components, area is reduced and fewer numbers of transistor devices are used to reduce cost. The shared components are selected such that the HV switch configuration provides functionality similar to traditional multiple HV switch configurations. Specifically, common logic shared across different branches of the single HV switch enables the single HV switch to provide multiple HV signals.

Abstract: An example of a circuit for generating high-voltage switching at an output terminal of the circuit includes a pair of n-type metal oxide semiconductor (NMOS) transistors responsive to input signals to generate a first voltage signal in a preset mode. The circuit also includes a predefined number of n-type cascode stages coupled between the output terminal and the pair of NMOS transistors to enable propagation of the first voltage signal to the output terminal. Further, the circuit includes a predefined number of p-type cascode stages coupled to the output terminal to enable propagation of the first voltage signal to an input voltage supply to the circuit. Furthermore, the circuit includes a first pair of cross-coupled p-type metal oxide semiconductor (PMOS) transistors coupled to the input voltage supply. The circuit includes a pair of PMOS transistors, coupled between the first pair of cross-coupled PMOS transistors and the p-type cascode stage.