Patents by Inventor Yao-Cheng Chuang

Yao-Cheng Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistance calibration method and related calibration system
    Patent number: 9608632
    Abstract: A resistance calibration method for a first resistor of a first module includes performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor and the calibration unit is coupled to the pad; obtaining a resistance value of the calibration unit after the resistance calibration; and calibrating a resistance value of the first resistor according to the resistance value of the calibration unit.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: March 28, 2017
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chien-Hsi Lee, Yao-Cheng Chuang
  • Resistance calibration method and related calibration system
    Publication number: 20170077927
    Abstract: A resistance calibration method for a first resistor of a first module includes performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor and the calibration unit is coupled to the pad; obtaining a resistance value of the calibration unit after the resistance calibration; and calibrating a resistance value of the first resistor according to the resistance value of the calibration unit.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 16, 2017
    Inventors: Chien-Hsi Lee, Yao-Cheng Chuang
  • Method and apparatus for self-calibrating driving capability and resistance of on-die termination
    Patent number: 9000850
    Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: April 7, 2015
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yao-Cheng Chuang, I-Huan Huang
  • METHOD AND APPARATUS FOR SELF-CALIBRATING DRIVING CAPABILITY AND RESISTANCE OF ON-DIE TERMINATION
    Publication number: 20140253250
    Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 11, 2014
    Inventors: Yao-Cheng Chuang, I-Huan Huang
  • Method of dynamically adjusting signal delay time of circuit system
    Patent number: 8171329
    Abstract: A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: May 1, 2012
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Te-Lin Ping, Yao-Cheng Chuang
  • METHOD OF DYNAMICALLY ADJUSTING SIGNAL DELAY TIME OF CIRCUIT SYSTEM
    Publication number: 20100180141
    Abstract: A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.
    Type: Application
    Filed: April 20, 2009
    Publication date: July 15, 2010
    Inventors: Te-Lin Ping, Yao-Cheng Chuang